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psd813f family psd813f zpsd813f zpsd813fv flash in-system-programmable microcontroller peripherals june, 1999 preliminary return to main menu 47280 kato road, fremont, california 94538 tel: 510-656-5400 fax: 510-657-8495 800-team-wsi (800-832-6974) web site: http://www.waferscale.com e-mail: info@waferscale.com
i psd813f family psd813f zpsd813f zpsd813fv flash in-system-programmable microcontroller peripherals table of contents 1.0 introduction ................................................................................................................ ...........................................1 2.0 key features ................................................................................................................ ........................................2 psd813f block diagram .......................................................................................................... .....................4 3.0 general information ......................................................................................................... .....................................5 4.0 psd813f family.............................................................................................................. .....................................5 5.0 psd813f architectural overview .............................................................................................. ...........................6 5.1 memory...................................................................................................................... .............................6 5.2 page register ............................................................................................................... ..........................6 5.3 plds ........................................................................................................................ ...............................6 5.4 i/o ports................................................................................................................... ...............................7 5.5 microcontroller bus interface ............................................................................................... ...................7 5.6 jtag port ................................................................................................................... ............................7 5.7 in-system programming ....................................................................................................... ..................8 5.8 power management............................................................................................................ ....................8 6.0 development system.......................................................................................................... ..................................9 7.0 psd813f pin descriptions .................................................................................................... .............................10 8.0 psd813f register description and address offset ............................................................................. ..............14 9.0 psd813f functional blocks ................................................................................................... ............................15 9.1 memory blocks ............................................................................................................... ......................15 9.1.1 main flash and optional secondary eeprom or flash boot memory description ..................15 9.1.2 sram ...................................................................................................................... ...................30 9.1.3 memory select signals..................................................................................................... ..........30 9.1.4 page register............................................................................................................. ................35 9.2 plds ........................................................................................................................ .............................36 9.2.1 decode pld (dpld) ......................................................................................................... .........38 9.2.2 complex pld (cpld) ........................................................................................................ ........38 9.3 microcontroller bus interface ............................................................................................... .................47 9.3.1 interfacing 16-bit mcus with two psd813f devices ................................................................47 9.3.2 psd813f interface to a multiplexed 8-bit bus ...........................................................................47 9.3.3 psd813f interface to a non-multiplexed 8-bit bus....................................................................47 9.3.4 data byte enable reference................................................................................................ ......50 9.3.5 microcontroller interface examples ........................................................................................ ....50 9.4 i/o ports................................................................................................................... .............................55 9.4.1 general port architecture................................................................................................. ..........55 9.4.2 port operating modes ...................................................................................................... ..........57 9.4.3 port configuration registers (pcrs) ....................................................................................... ..60 9.4.4 port data registers ....................................................................................................... .............63 9.4.5 ports a and b ? functionality and structure ............................................................................6 4 9.4.6 port c ? functionality and structure .................................................................................... ....66 9.4.7 port d ? functionality and structure .................................................................................... ....66 9.5 power management............................................................................................................ ..................70 9.5.1 automatic power down (apd) unit and power down mode .....................................................70 9.5.2 other power saving options................................................................................................ ......74 9.5.3 reset input ............................................................................................................... ..................75
ii for additional information, call 800-team-wsi (800-832-6974). fax: 510-657-8495 web site: http://www.waferscale.com e-mail: info@waferscale.com psd813f family psd813f zpsd813f zpsd813fv flash in-system-programmable microcontroller peripherals table of contents (cont.) 9.6 programming in-circuit using the jtag interface ............................................................................. ..76 9.6.1 standard jtag signals..................................................................................................... .........77 9.6.2 jtag extensions........................................................................................................... .............78 9.6.3 security and flash memories and eeprom protection ............................................................78 absolute maximum ratings....................................................................................................... ..................................79 ad/dc parameters............................................................................................................... .......................................80 example of psd813f typical power calculation at v cc = 5.0 v.......................................................................81 example of zpsd813f typical power calculation at v cc = 5.0 v.....................................................................82 psd813f/zpsd813f dc characteristics (5 v 10% versions) .......................................................................8 3 psd813f dc characteristics (i cc ).....................................................................................................................84 zpsd813f dc characteristics (i cc )...................................................................................................................84 psd813f ad/dc parameters ? cpld timing parameters (5 v 10% versions) ...........................................85 zpsd813fv dc characteristics (3 v 10% versions)............................................................................... .......95 zpsd813fv ac/dc parameters ? cpld timing parameters (3 v 10% versions) .....................................96 timing diagrams ................................................................................................................ .......................................104 programming .................................................................................................................... .........................................111 psd813f pin assignments ........................................................................................................ ...............................112 psd813f package information .................................................................................................... .............................114 selector guide................................................................................................................. ..........................................117 part number construction ....................................................................................................... ..................................118 ordering information........................................................................................................... .......................................118 temporary exceptions to specifications ......................................................................................... ..........................122 product revisions.............................................................................................................. ........................................124 worldwide sales, service and technical support................................................................................. ....................128
iii psd813f family preliminary for additional information, call 800-team-wsi (800-832-6974). fax: 510-657-8495 web site: http://www.waferscale.com e-mail: info@waferscale.com
1 1.0 introduction preliminary programmable peripheral psd813f family psd813f zpsd813f zpsd813fv flash in-system-programmable microcontroller peripherals the psd813f family of programmable microcontroller (mcu) peripherals brings in-system-programmability (isp) to flash memory and programmable logic. the result is a simple and flexible solution for embedded designs. psd813f devices combine many of the peripheral functions found in mcu based applications: 1 mbit of flash memory a second eeprom or flash memory over 3,000 gates of flash programmable logic sram reconfigurable i/o ports programmable power management. for lowest power operation refer to the zpsd813f/813fv products. updated june 18, 1999. see page 124. psd813f devices integrate an optimized micro controller macro cell ?logic architecture called the micro ? cell tm . the micro ? cell was created to address the unique requirements of embedded system designs. it allows direct connection between the system address/data bus and the internal psd registers to simplify communication between the mcu and other supporting devices.
psd813f family preliminary 2 1.0 introduction (cont.) please refer to the revision block at the end of this document for updated information. the psd813f family includes a jtag serial programming interface to allow in-system- programming of the entire device . this feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. using wsis special fast-jtag programming, a design can be programmed into the psd813f in as little as seven seconds. the innovative flash psd813f family solves key problems faced by designers when managing discrete flash memory devices, such as: first-time programming complex address decoding simultaneous read and write to flash. the psd813fs serial jtag interface allows in-system-programming and eliminates the need for a boot eprom or an external programmer. to simplify flash updates, the psd813f1, psd813f2, and psd813f4 devices perform program execution out of a secondary eeprom (f1) or flash (f2/f4) memory block while the main flash memory is being updated. this solution avoids the complicated overhead circuitry and software necessary to implement in-system flash memory updates. psdsoft wsis software development tool now has the ability to generate ansi-c compliant code for use with your target mcu. the code generated allows you to manipulate the non-volatile memory (nvm) within the psd. code examples are also provided for: flash isp via the uart of the host mcu memory paging to execute code across several psd memory pages loading, reading, and manipulation of psd micro ? cells by the mcu the psd813f is available in a 52-pin plcc package and a 64-pin plastic thin quad flatpack (tqfp) package. o a simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. the bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. a partial list of the mcu families supported include: intel 8031, 80196, 80186, 80c251, and 80386ex motorola 68hc11, 68hc16, 68hc12, and 683xx philips 8031 and 8051xa zilog z80 and z8 neuron 3150 chip tm . o internal 1 mbit flash memory. this is the main flash memory. it is divided into eight equal-sized blocks that can be accessed with user-specified addresses. o optional internal secondary 256 kbit eeprom or flash boot memory. it is divided into four equal-sized blocks that can be accessed with user-specified addresses. this secondary memory brings the ability to execute code and update the main flash concurrently. o optional 16 kbit scratchpad sram. the srams contents can be protected from a power failure by connecting an external battery. 2.0 key features
preliminary psd813f family 3 o optional 64 byte one time programmable (otp) memory that can be used for product configuration and calibration. o cpld with 16 output micro ? cells (omcs) and 24 input micro ? cells (imcs). the cpld may be used to efficiently implement a variety of logic functions for internal and external control. examples include state machines, loadable shift registers, and loadable counters. o decode pld (dpld) that decodes address for selection of internal memory blocks. the dpld can also be used to generate external chip selects. o 27 individually configurable i/o port pins that can be used for the following functions: mcu i/os pld i/os latched mcu address output special function i/os. 16 of the i/o ports may be configured as open-drain outputs. o standby current as low as 50 ? for 5 v devices, 25 ? for 3 v devices. o built-in jtag compliant serial port allows full-chip in-system programmability (isp). with it, you can program a blank device or reprogram a device in the factory or the field. o internal page register that can be used to expand the microcontroller address space by a factor of 256. o internal programmable power management unit (pmu) that supports a low power mode called power down mode. the pmu can automatically detect a lack of microcontroller activity and put the psd813f into power down mode. o erase/write cycles: flash memory ?100,000 minimum eeprom ?10,000 minimum pld ?1,000 minimum 2.0 key features (cont.)
psd813f family preliminary 4 prog. mcu bus intrf. adio port cntl0, cntl1, cntl2 ad0 ?ad15 clkin clkin clkin pld input bus prog. port port a prog. port port b power mangmt unit 1 mbit main flash memory 8 sectors vstdby pa0 ?pa7 pb0 ?pb7 prog. port port c prog. port port d pc0 ?pc7 pd0 ?pd2 address/data/control bus port a ,b & c 3 ext cs to port d 24 input micro ? cells port a ,b & c 73 73 256 kbit secondary memory (boot or data) 4 sectors eeprom ?f1 flash ?f2, f4 none ?f3, f5 16 kbit battery backup sram none - f4, f5 runtime control and i/o registers sram select perip i/o mode selects micro ? cell feedback or port input csiop flash isp cpld (cpld) 16 output micro ? cells flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pc2 ) page register embedded algorithm sector selects sector selects global config. & security figure 1. psd813f block diagram
preliminary psd813f family 5 3.0 general information the psd813f series architecture allows in-system programming of all memory, pld logic and device configuration. the embedded input and output micro ? cells enable efficient implementation of user defined logic functions that require both software and hardware interaction. the devices eliminate the need for discrete ?lue?logic, and allow the development of entire systems using only a few highly integrated devices. 4.0 psd813f family there are 5 variants in the psd813f family. all psd813f devices provide these base features: 1 mbit main flash memory, jtag port, cpld, dpld, power management, and 27 i/o pins. the following statements show what each psd813f family member adds to this set of basic features: o psd813f1 adds 256 kbits eeprom and 16 kbits sram to the base feature set. these independent memories can operate concurrently with each other and with the main flash memory. the psd813f1 also adds 64 bytes of otp memory for any use (product serial number, calibration constants, etc.). once written, the otp memory can never be altered. o psd813f2 adds 256 kbits flash memory and 16 kbits sram to the base feature set. these independent memories can operate concurrently with each other and with the main flash memory. o psd813f3 adds 16 kbits sram to the base feature set. this independent memory can operate concurrently with the main flash memory. o psd813f4 adds 256 kbits flash memory to the base feature set. this independent memory can operate concurrently with the main flash memory. o psd813f5 no additions to base feature set. the following table summarizes all the devices in the psd813f family. the zpsd family members offer extra power savings features (slight penalty to memory access time and pld propagation delay). part # flash additional no. of serial isp main memory memory for psd813f i/o micro ? cells jtag/isc kbit boot and/or data sram turbo supply family device pins input/output port (8 sectors) (4 sectors) kbit mode voltage psd813f psd813f1 27 24/16 yes 1024 256 kbit eeprom 16 5v psd813f2 27 24/16 yes 1024 256 kbit flash 16 5v psd813f3 27 24/16 yes 1024 none 16 5v psd813f4 27 24/16 yes 1024 256 k bit flash none 5v psd813f5 27 24/16 yes 1024 none none 5v zpsd813f ZPSD813F1 27 24/16 yes 1024 256 kbit eeprom 16 yes 5v zpsd813f2 27 24/16 yes 1024 256 kbit flash 16 yes 5v zpsd813f3 27 24/16 yes 1024 none 16 yes 5v zpsd813f4 27 24/16 yes 1024 256 k bit flash none yes 5v zpsd813f5 27 24/16 yes 1024 none none yes 5v zpsd813fv ZPSD813F1v 27 24/16 yes 1024 256 kbit eeprom 16 yes 3v zpsd813f2v 27 24/16 yes 1024 256 kbit flash 16 yes 3v zpsd813f3v 27 24/16 yes 1024 none 16 yes 3v zpsd813f4v 27 24/16 yes 1024 256 k bit flash none yes 3v zpsd813f5v 27 24/16 yes 1024 none none yes 3v table 1. psd813f product matrix
psd813f family preliminary 6 psd813f devices contain several major functional blocks. figure 1 on page 3 shows the architecture of the psd813f device family. the functions of each block are described briefly in the following sections. many of the blocks perform multiple functions and are user configurable. 5.1 memory the psd813f contains the following memories: a 1 mbit flash an optional secondary 256 kbit eeprom or flash boot memory an optional 16 kbit sram. each of the memories is briefly discussed in the following paragraphs. a more detailed discussion can be found in section 9. the 1 mbit flash is the main memory of the psd813f. it is divided into eight equally-sized sectors that are individually selectable. the optional 256 kbit eeprom or flash is divided into four equally-sized sectors. each sector is individually selectable. the optional 16 kbit sram is intended for use as a scratchpad memory or as an extension to the microcontroller sram. if an external battery is connected to the psd813fs vstby pin, data will be retained in the event of a power failure. each block of memory can be located in a different address space as defined by the user. the access times for all memory types includes the address latching and dpld decoding time. 5.2 page register the eight-bit page register expands the address range of the microcontroller by up to 256 times.the paged address can be used as part of the address space to access external memory and peripherals or internal memory and i/o. the page register can also be used to change the address mapping of blocks of flash memory into different memory spaces for in-circuit reprogramming. 5.3 plds the device contains two pld blocks, each optimized for a different function, as shown in table 2. the functional partitioning of the plds reduces power consumption, optimizes cost/performance, and eases design entry. the decode pld (dpld) is used to decode addresses and generate chip selects for the psd813f internal memory and registers. the cpld can implement user-defined logic functions. the dpld has combinatorial outputs. the cpld has 16 output micro ? cells and 3 combinatorial outputs. the psd813f also has 24 input micro ? cells that can be configured as inputs to the plds. the plds receive their inputs from the pld input bus and are differentiated by their output destinations, number of product terms, and micro ? cells. the plds consume minimal power by using zero-power design techniques. the speed and power consumption of the pld is controlled by the turbo bit (zpsd only) in the pmmr0 register and other bits in the pmmr2 registers. these registers are set by the microcontroller at runtime. there is a slight penalty to pld propagation time when invoking the zpsd features. 5.0 psd813f architectural overview name abbreviation inputs outputs product terms decode pld dpld 73 17 42 complex pld cpld 73 19 140 table 2. pld i/o table
preliminary psd813f family 7 psd813f architectural overview (cont.) 5.4 i/o ports the psd813f has 27 i/o pins divided among four ports (port a, b, c, and d). each i/o pin can be individually configured for different functions. ports a, b, c and d can be configured as standard mcu i/o ports, pld i/o, or latched address outputs for microcontrollers using multiplexed address/data busses. the jtag pins can be enabled on port c for in-system programming (isp). ports a and b can also be configured as a data port for a non-multiplexed bus or multiplexed address/data buses for certain types of 16-bit microcontrollers. 5.5 microcontroller bus interface the psd813f easily interfaces with most 8-bit microcontrollers that have either multiplexed or non-multiplexed address/data busses. the device is configured to respond to the microcontrollers control signals, which are also used as inputs to the plds. where there is a requirement to use a 16-bit data bus to interface to a 16-bit microcontroller, two psds must be used. section 9.3.5 contains microcontroller interface examples. 5.6 jtag port in-system programming can be performed through the jtag pins on port c. this serial interface allows complete programming of the entire psd813f device. a blank device can be completely programmed. the jtag signals (tms, tck, tstat, terr, tdi, tdo) can be multiplexed with other functions on port c. table 3 indicates the jtag signals pin assignments. port c pins jtag signal pc0 tms pc1 tck pc3 tstat pc4 terr pc5 tdi pc6 tdo table 3. jtag signals on port c
psd813f family preliminary 8 5.7 in-system programming using the jtag signals on port c, the entire psd813f device can be programmed or erased without the use of the microcontroller. the main flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the optional eeprom, flash boot memory, or sram. the optional eeprom or flash boot memory can be programmed the same way by executing out of the main flash memory. the pld logic or other psd813f configuration can be programmed through the jtag port or a device programmer. table 4 indicates which programming methods can program different functional blocks of the psd813f. psd813f architectural overview (cont.) jtag device in-system parallel functional block programming programmer programming main flash memory yes yes yes optional eeprom/flash boot yes yes yes memory pld array (dpld yes yes no and cpld) psd configuration yes yes no optional otp row no yes yes table 4. methods of programming different functional blocks of the psd813f 5.8 power management unit the power management unit (pmu) in the psd813f gives the user control of the power consumption on selected functional blocks based on system requirements. the pmu includes an automatic power down unit (apd) that will turn off device functions due to microcontroller inactivity. the apd unit has a power down mode that helps reduce power consumption. the zpsd813f also has some bits that are configured at run-time by the mcu to reduce power consumption of the cpld. the turbo bit in the pmmr0 register can be turned off and the cpld will latch its outputs and go to sleep until the next transition on its inputs. additionally, bits in the pmmr2 register can be set by the mcu to block signals from entering the cpld to reduce power consumption. see section 9.5.
preliminary psd813f family 9 psd configuration psd fitter psd simulator psd programmer *.obj file zpld description configure mcu bus interface and other psd attributes logic synthesis and fitting psdsilos iii device simulation (optional) psdpro, or flashlink (jtag) address translation and memory mapping psdabel modify abel template file or generate new file psd tools generate c code specific to psd functions user's choice of microcontroller compiler/linker *.obj and *.svf files available for 3rd party programmers (conventional or jtag-isc) firmware hex or s-record format figure 2. psdsoft development tools 6.0 development system the psd813f family is supported by the windows-based psdsoft development system. the psdsoft design flow is shown in figure 2. the pld design entry is done using psdabel, which creates a minimized logic implementation, and provides logic simulation of the plds. the psd813f mcu bus interface and i/o port configuration are entered in psd configuration. psdsoft can generate ansi c functions specific to the psd. the user can merge these c functions with their own, and then compile and link it using any embedded c compiler on the market. psd fitter is comprised of a fitter and address translator. it generates a programming data file (.obj) based on psd configuration data, the psdabel file, and the microcontroller firmware. the object file can be downloaded to a programmer or to psd simulator for device-level simulation. psdsoft offers direct support for three wsi device programmers, psdpro, magicpro iii, and flashlink (jtag). psdsoft makes available two types of files to support third party programmers. first, the *.obj file is in intel hex format, and is compatible with conventional device programmers. second, the *.svf file is a serial vector format file for jtag-isc device programmers.
psd813f family preliminary 10 the following table describes the pin names and pin functions of the psd813f. pins that have multiple names and/or functions are defined using psd configuration. 7.0 table 5. psd813f pin descriptions pin name pin* type description adio0-7 30-37 i/o this is the lower address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect ad[0:7] to this port. 2. if your mcu does not have a multiplexed address/data bus, or you are using an 80c251 in page mode, connect a[0:7] to this port. 3. if you are using an 80c51xa in burst mode, connect a4/d0 through a11/d7 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. adio8-15 39-46 i/o this is the upper address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect a[8:15] to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a[8:15] to this port. 3. if you are using an 80c251 in page mode, connect ad[8:15] to this port. 4. if you are using an 80c51xa in burst mode, connect a12/d8 through a19/d15 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. cntl0 47 i the following control signals can be connected to this port, based on your mcu: 1. wr ?active-low write input. 2. r_w ?active-high read/active low write input. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl1 50 i the following control signals can be connected to this port, based on your mcu: 1. rd ?active-low read input. 2. e ?e clock input. 3. ds ?active-low data strobe input. 4. psen ?connect psen to this port when it is being used as an active-low read signal. for example, when the 80c251 outputs more than 16 address bits, psen is actually the read signal. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations.
preliminary psd813f family 11 pin name pin* type description cntl2 49 i this port can be used to input the psen (program select enable) signal from any mcu that uses this signal for code exclusively. if your mcu does not output a program select enable signal, this port can be used as a generic input. this port is connected to the plds. reset 48 i active low reset input. resets i/o ports, pld micro ? cells and some of the configuration registers. must be active at power up. pa0 29 i/o these pins make up port a. these port pins are configurable pa1 28 and can have the following functions: pa2 27 1. mcu i/o ?write to or read from a standard output or pa3 25 input port. pa4 24 2. cpld micro ? cell (mcellab0-7) outputs. pa5 23 3. inputs to the plds. pa6 22 4. latched address outputs (see table 6). pa7 21 5. address inputs. for example, pa0-3 could be used for a[0:3] when using an 80c51xa in burst mode. 6. as the data bus inputs d[0:7] for non-multiplexed address/data bus mcus. 7. d0/a16-d3/a19 in m37702m2 mode. 8. peripheral i/o mode. note: pa0-3 can only output cmos signals with an option for high slew rate. however, pa4-7 can be configured as cmos or open drain outputs. pb0 7 i/o these pins make up port b. these port pins are configurable pb1 6 and can have the following functions: pb2 5 1. mcu i/o ?write to or read from a standard output or pb3 4 input port. pb4 3 2. cpld micro ? cell (mcellab0-7 or mcellbc0-7) outputs. pb5 2 3. inputs to the plds. pb6 52 4. latched address outputs (see table 6). pb7 51 note: pb0-3 can only output cmos signals with an option for high slew rate. however, pb4-7 can be configured as cmos or open drain outputs. pc0 20 i/o pc0 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc0) output. 3. input to the plds. 4. tms input** for the jtag interface. this pin can be configured as a cmos or open drain output. pc1 19 i/o pc1 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc1) output. 3. input to the plds. 4. tck input** for the jtag interface. this pin can be configured as a cmos or open drain output. table 5. psd813f pin descriptions (cont.)
psd813f family preliminary 12 table 5. psd813f pin descriptions (cont.) pin name pin* type description pc2 18 i/o pc2 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc2) output. 3. input to the plds. 4. vstby ?sram standby voltage input for sram battery backup. this pin can be configured as a cmos or open drain output. pc3 17 i/o pc3 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc3) output. 3. input to the plds. 4. tstat output** for the jtag interface. 5. rdy/bsy output for in-system parallel programming. this pin can be configured as a cmos or open drain output. pc4 14 i/o pc4 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc4) output. 3. input to the plds. 4. terr output** for the jtag interface. 5. vbaton ?battery backup indicator output. goes high when power is being drawn from an external battery. this pin can be configured as a cmos or open drain output. pc5 13 i/o pc5 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc5) output. 3. input to the plds. 4. tdi input** for the jtag interface. this pin can be configured as a cmos or open drain output. pc6 12 i/o pc6 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc6) output. 3. input to the plds. 4. tdo output** for the jtag interface. this pin can be configured as a cmos or open drain output.
preliminary psd813f family 13 table 5. psd813f pin descriptions (cont.) pin name pin* type description pc7 11 i/o pc7 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. cpld micro ? cell (mcellbc7) output. 3. input to the plds. 4. dbe ?active-low data byte enable input from 68hc912 type mcus. this pin can be configured as a cmos or open drain output. pd0 10 i/o pd0 pin of port d. this port pin can be configured to have the following functions: 1. ale/as input latches address output from the mcu. 2. mcu i/o ?write or read from a standard output or input port. 3. input to the plds. 4. cpld output (external chip select). pd1 9 i/o pd1 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. input to the plds. 3. cpld output (external chip select). 4. clkin ?clock input to the cpld micro ? cells, the automatic power-down units power-down counter, and the cpld and array. pd2 8 i/o pd2 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o ?write to or read from a standard output or input port. 2. input to the plds. 3. cpld output (external chip select). 4. csi ?chip select input. when low, the mcu can access the psd memory and i/o. when high, the psd memory blocks are disabled to conserve power. v cc 15, 38 power pins gnd 1,16,26 ground pins port a port b microcontroller port a (3:0) port a (7:4) port b (3:0) port b (7:4) 8051xa (8-bit) n/a address [7:4] address [11:8] n/a 80c251 (page mode) n/a n/a address [11:8] address [15:12] all other 8-bit multiplexed address [3:0] address [7:4] address [3:0] address [7:4] 8-bit non-multiplexed bus n/a n/a address [3:0] address [7:4] table 6. i/o port latched address output assignments* n/a = not applicable * * refer to the i/o port section on how to enable the latched address output function. * * the pin numbers in this table are for the plcc package only. see the package information section for pin numbers on other package types. ** these functions can be multiplexed with other functions.
psd813f family preliminary 14 table 7 shows the offset addresses to the psd813f registers relative to the csiop base address. the csiop space is the 256 bytes of address that is allocated by the user to the internal psd813f registers. table 7 provides brief descriptions of the registers in csiop space. for a more detailed description, refer to section 9. 8.0 psd813f register description and address offset register name port a port b port c port d other* description data in 00 01 10 11 reads port pin as input, mcu i/o input mode control 02 03 selects mode between mcu i/o or address out stores data for output data out 04 05 12 13 to port pins, mcu i/o output mode direction 06 07 14 15 configures port pin as input or output configures port pins as either cmos or open drive select 08 09 16 17 drain on some pins, while selecting high slew rate on other pins. input micro ? cell 0a 0b 18 reads input micro ? cells reads the status of the enable out 0c 0d 1a 1b output enable to the i/o port driver read ? reads output of output micro ? cells ab micro ? cells ab 20 20 write ? loads micro ? cell flip-flops read ? reads output of output micro ? cells bc micro ? cells bc 21 21 write ? loads micro ? cell flip-flops mask 22 22 blocks writing to the micro ? cells ab output micro ? cells ab mask 23 23 blocks writing to the micro ? cells bc output micro ? cells bc flash protection c0 read only ?flash sector protection psd/ee read only ?psd security protection c2 and eeprom/flash boot sector protection jtag enable c7 enables jtag port pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register places psd memory vm e2 areas in program and/or data space on an individual basis. table 7. register address offset * other registers that are not part of the i/o ports.
preliminary psd813f family 15 9.0 the psd813f functional blocks as shown in figure 1, the psd813f consists of six major types of functional blocks: o memory blocks o pld blocks o bus interface o i/o ports o power management unit o jtag interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. 9.1 memory blocks the psd813f has the following memory blocks: the main flash memory optional secondary eeprom or flash boot memory optional sram. the memory select signals for these blocks originate from the decode pld (dpld) and are user-defined in psdsoft. table 8 summarizes which versions of the psd813f contain which memory blocks. device main flash eeprom flash boot memory sram 128kb 32kb 32k 2kb psd813f1 yes yes no yes psd813f2 yes no yes yes psd813f3 yes no no yes psd813f4 yes no yes no psd813f5 yes no no no table 8. memory blocks 9.1.1 main flash and optional secondary eeprom or flash boot memory description the 1 mbit main flash memory block is divided evenly into eight 16 kbyte sectors. the optional eeprom or flash boot memory is divided into four sectors of eight kbytes each. each sector of either memory can be separately protected from program and erase operations. flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte. flash sector erasure may be suspended while data is read from other sectors of memory and then resumed after reading. eeprom may be programmed byte-by-byte or sector-by-sector, and erasing is automatic and transparent. the integrity of the data can be secured with the help of software data protection (sdp). any write operation to the eeprom is inhibited during the first five milliseconds following power-up. during a program or erase of flash, or during a write of the eeprom, the status can be output on the rdy/bsy pin of port c3. this pin is set up using psdsoft configuration.
psd813f family preliminary 16 9.1.1.1 memory block selects the decode pld in the psd813f generates the chip selects for all the internal memory blocks (refer to the pld section). each of the eight flash memory sectors have a flash select signal (fs0-fs7) which can contain up to three product terms. each of the optional four eeprom or flash boot memory sectors have a select signal (ees0-3 or csboot0-3) which can contain up to three product terms. having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. when using a microcontroller with separate program and data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other. 9.1.1.2 the ready/busy pin (pc3) pin pc3 can be used to output the ready/busy status of the psd813f. the output on the pin will be a ??(busy) when flash or eeprom memory blocks are being written to, or when the flash memory block is being erased. the output will be a ??(ready) when no write or erase operation is in progress. 9.1.1.3 memory operation the main flash and optional eeprom or flash boot memories are addressed through the microcontroller interface on the psd813f device. the microcontroller can access these memories in one of two ways: o the microcontroller can execute a typical bus write or read operation just as it would if accessing a ram or rom device using standard bus cycles. o the microcontroller can execute a specific instruction that consists of several write and read operations. this involves writing specific data patterns to special addresses within the flash or eeprom to invoke an embedded algorithm. these instructions are summarized in table 9. typically, flash memory can be read by the microcontroller using read operations, just as it would read a rom device. however, flash memory can only be erased and programmed with specific instructions. for example, the microcontroller cannot write a single byte directly to flash memory as one would write a byte to ram. to program a byte into flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. this status test is achieved by a read operation or polling the rdy/busy pin (pc3). the flash memory can also be read by using special instructions to retrieve particular flash device information (sector protect status and id). the eeprom is a bit different. data can be written to eeprom memory using write operations, like writing to a ram device, but the status of each write event must be checked by the microcontroller. a write event can be one to 64 contiguous bytes. the status test is very similar to that used for flash memory (read operation or rdy/busy). optionally, the eeprom memory may be put into a software data protect (sdp) mode where it requires instructions, rather than operations, to alter its contents. sdp mode makes writing to eeprom much like writing to flash memory. the psd813f functional blocks (cont.)
preliminary psd813f family 17 the psd813f functional blocks (cont.) 9.1.1.3.1 instructions an instruction is defined as a sequence of specific operations. each received byte is sequentially decoded by the psd and not executed as a standard write operation. the instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. some instructions are structured to include read operations after the initial write operations. the sequencing of any instruction must be followed exactly. any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory will reset the device logic into a read array mode (flash memory reads like a rom device). an invalid combination or time-out while addressing the eeprom block will cause the offending byte to be interpreted as a single operation. the psd813f supports these instructions (see table 9): flash memory: o erase memory by chip or sector o suspend or resume sector erase o program a byte o reset to read array mode o read flash identifier value o read sector protection status optional eeprom: o write data to otp row o read data from otp row o power down memory o enable software data protect (sdp) o disable sdp o return from read otp row read mode or power down mode. these instructions are detailed in table 9. for efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. the coded cycles consist of writing the data aah to address x555h during the first cycle and data 55h to address xaaah during the second cycle. address lines a15-a12 are don? cares during the instruction write cycles. however, the appropriate sector select signal (fsi, eesi, or csbooti) must be selected.
psd813f family preliminary 18 flash sector eeprom select sector (fsi, select csbooti) instruction (eesi) (note 2) cycle 1 cycle 2 cycle 3 cycle 4 cycle5 cycle 6 cycle 7 read read aah 55h 90h identifier flash 01 @x555h @xaaah @x555h with identifier (a6,a1,a0 (note 3, 5) at 0,0,1) read otp row 1 0 aah 55h 90h read read read (note 4) @x555h @xaaah @x555h byte 1 byte 2 byte n read read sector aah 55h 90h identifier protection 01 @x555h @xaaah @x555h with status (a6,a1,a0 (notes 3, 5) at 0,1,0) program a 0 1 aah 55h a0h data flash byte @x555h @xaaah @x555h @ address (note 5) erase one aah 55h 80h aah 55h 30h 30h flash sector 0 1 @x555h @xaaah @x555h @x555h @xaaah @ sector @ sector (note 5) address address(1) erase the 0 1 aah 55h 80h aah 55h 10h whole flash @x555h @xaaah @x555h @x555h @xaaah @x555h (note 5) suspend sector b0h erase 0 1 @ any (note 5) address resume 30h sector erase 0 1 @ any (note 5) address eeprom power 10 aah 55h 30h down (note 4) @x555h @xaaah @x555h sdp enable/ 1 0 aah 55h a0h write write write eeprom write @x555h @xaaah @x555h byte 1 byte 2 byte n (note 4) sdp disable 1 0 aah 55h 80h aah 55h 20h (note 4) @x555h @xaaah @x555h @x555h @xaaah @x555h write in otp 1 0 aah 55h b0h write write write row (notes 4, 6) @x555h @xaaah @x555h byte 1 byte 2 byte n return (from otp f0h @ read or eeprom 1 0 any power-down) address (note 4) aah 55h f0h reset 01 @x555h @xaaah @ any (notes 3, 5) address reset f0h (short instruction) 0 1 @ any (note 5) address table 9. instructions notes: 1. additional sectors to be erased must be entered within 80 ?. a sector address is any address within the sector. 2. flash and eeprom sector selects are active high. addresses a15-a12 are don? cares in instruction bus cycles. 3. the reset instruction is required to return to the normal read array mode if dq5 goes high or after reading the flash identifier or protection status. 4. the mcu cannot invoke these instructions while executing code from eeprom. the mcu must be operating from some other memory when these instructions are performed. 5. the mcu cannot invoke these instructions while executing code from the same flash memory for which the instruction is intended. the mcu must operate from some other memory when these instructions are executed. 6. writing to otp row is allowed only when sdp mode is disabled. the psd813f functional blocks (cont.)
preliminary psd813f family 19 the psd813f functional blocks (cont.) 9.1.1.4 power down instruction and power up condition 9.1.1.4.1 eeprom power down instruction (psd813f1 only) the eeprom can enter power down mode with the help of the eeprom power down instruction (see table 9). once the eeprom power down instruction is decoded, the eeprom memory cannot be accessed unless a return instruction (also in table 9) is decoded. alternately, this power down mode will automatically occur when the apd circuit is triggered (see section 9.5.1). therefore, this instruction is not required if the apd circuit is used. 9.1.1.4.2 power-up condition the psd813f internal logic is reset upon power-up to the read array mode. any write operation to the eeprom is inhibited during the first 5 msec following power-up. the fsi and eesi/csbooti select signals, along with the write strobe signal, must be in the false state during power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. any write cycle initiation is locked when v cc is below vlko. 9.1.1.5 read under typical conditions, the microcontroller may read the flash, eeprom, or flash boot memories using read operations just as it would a rom or ram device. alternately, the microcontoller may use read operations to obtain status information about a program or erase operation in progress. lastly, the microcontroller may use instructions to read special data from these memories. the following sections describe these read functions. 9.1.1.5.1 read the contents of memory main flash and flash boot memories are placed in the read array mode after power-up, chip reset, or a reset flash instruction (see table 9). the microcontroller can read the memory contents of main flash, optional eeprom, or optional flash boot by using read operations any time the read operation is not part of an instruction sequence. 9.1.1.5.2 read the main flash memory identifier the main flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 9). during the read operation, address bits a6, a1, and a0 must be 0,0,1, respectively, and the appropriate sector select signal (fsi) must be active. see section 9.1.1.9.3 for information on how to use the flash memory identifier. 9.1.1.5.3 read the main flash memory sector protection status the main flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 9). during the read operation, address bits a6, a1, and a0 must be 0,1,0, respectively, while the chip select fsi designates the flash sector whose protection has to be verified. the read operation will produce 01h if the flash sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (main flash, eeprom, or boot flash) can be read by the microcontroller accessing the flash protection and psd/ee protection registers in psd i/o space. see section 9.1.1.9.1 for register definitions.
psd813f family preliminary 20 9.1.1.5.4 read the otp row (psd813f1 only) there are 64 bytes of one-time-programmable (otp) memory that reside in eeprom. these 64 bytes are in addition to the 32 kbytes of eeprom memory. a read of the otp row is done with an instruction composed of at least 4 operations: 3 specific write operations and one to 64 read operations (see table 9). during the read operation(s), address bit a6 must be zero, while address bits a5-a0 define the otp row byte to be read while any eeprom sector select signal (eesi) is active. after reading the last byte, an eeprom return instruction must be executed (see table 9). 9.1.1.5.5 read the erase/program status bits the psd813f provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of flash memory. bits are also available to show the status of writes to eeprom. these status bits minimize the time that the microcontroller spends performing these tasks and are defined in table 10. the status bits can be read as many times as needed. fsi/ csbooti eesi dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 data toggle error erase flash v ih v il polling flag flag x time- x x x out eeprom v il v ih data toggle xxxxxx polling flag table 10. status bit notes: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq7-dq0 represent the data bus bits, d7-d0. 3. fsi/csbooti and eesi are active high. the psd813f functional blocks (cont.) for flash memory, the microcontroller can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. see section 9.1.1.7 for details. for eeprom not in sdp mode, the microcontroller can perform a read operation to obtain these status bits just after a data write operation. the microcontroller may write one to 64 bytes before reading the status bits. see section 9.1.1.6 for details. for eeprom in sdp mode, the microcontroller will perform a read operation to obtain these status bits while an sdp write instruction is being executed by the embedded algorithm. see section 9.1.1.1.3 for details.
preliminary psd813f family 21 the psd813f functional blocks (cont.) 9.1.1.5.6 data polling flag dq7 when erasing or programming the flash memory (or when writing into the eeprom memory), bit dq7 outputs the complement of the bit being entered for programming/writing on dq7. once the program instruction or the write operation is completed, the true logic value is read on dq7 (in a read operation). flash memory specific features: o data polling is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). it must be performed at the address being programmed or at an address within the flash sector being erased. o during an erase instruction, dq7 outputs a ?? after completion of the instruction, dq7 will output the last bit programmed (it is a ??after erasing). o if the byte to be programmed is in a protected flash sector, the instruction is ignored. o if all the flash sectors to be erased are protected, dq7 will be set to ??for about 100 ?, and then return to the previous addressed byte. no erasure will be performed. 9.1.1.5.7 toggle flag dq6 the psd813f offers another way for determining when the eeprom write or the flash memory program instruction is completed. during the internal write operation and when either the fsi or eesi/csbooti is true, the dq6 will toggle from ??to ??and ??to ??on subsequent attempts to read any byte of the memory. when the internal cycle is complete, the toggling will stop and the data read on the data bus d0-7 is the addressed memory byte. the device is now accessible for a new read or write operation. the operation is finished when two successive reads yield the same output data. flash memory specific features: o the toggle bit is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). o if the byte to be programmed belongs to a protected flash sector, the instruction is ignored. o if all the flash sectors selected for erasure are protected, dq6 will toggle to ??for about 100 ? and then return to the previous addressed byte. 9.1.1.5.8 error flag dq5 during a correct program or erase, the error bit will set to ?? this bit is set to ??when there is a failure during flash byte programming, sector erase, or bulk erase. in the case of flash programming, the error bit indicates the attempt to program a flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. the error bit may also indicate a timeout condition while attempting to program a byte. in case of an error in flash sector erase or byte program, the flash sector in which the error occurred or to which the programmed byte belongs must no longer be used. other flash sectors may still be used. the error bit resets after the reset instruction. 9.1.1.5.9 erase time-out flag dq3 (flash memory only) the erase timer bit reflects the time-out period allowed between two consecutive sector erase instructions. the erase timer bit is set to ??after a sector erase instruction for a time period of 100 ? + 20% unless an additional sector erase instruction is decoded. after this time period or when the additional sector erase instruction is decoded, dq3 is set to ??
psd813f family preliminary 22 9.1.1.6 writing to the optional eeprom data may be written a byte at a time to the eeprom using simple write operations, much like writing to an sram. unlike sram though, the completion of each byte write must be checked before the next byte is written. to speed up this process, the psd813f offers a page write feature to allow writing of several bytes before checking status. to prevent inadvertent writes to eeprom, the psd813f offers a software data protect (sdp) mode. once enabled, sdp forces the mcu to ?nlock?the eeprom before altering its contents, much like flash memory programming. 9.1.1.6.1 write a byte to eeprom a write operation is initiated when an eeprom select signal (eesi) is true and the write strobe signal (wr) into the psd813f is true. if the psd813f detects no additional writes within 120 ?ec, an internal storage operation is initiated. internal storage to eeprom memory technology typically takes a few milliseconds to complete. the status of the write operation is obtained by the mcu reading the data polling or toggle bits (as detailed in section 9.1.1.5), or the ready/busy output pin (section 9.1.1.2). keep in mind that the mcu does not need to erase a location in eeprom before writing it. erasure is performed automatically as an internal process. 9.1.1.6.2 write a page to eeprom writing data to eeprom using page mode is more efficient than writing one byte at a time. the psd813f eeprom has a 64 byte volatile buffer that the mcu may fill before an internal eeprom storage operation is initiated. page mode timing approaches a 64:1 advantage over the time it takes to write individual bytes. to invoke page mode, the mcu must write to eeprom locations within a single page, with no more than 120 ?ec between individual byte writes. a single page means that address lines a14 to a6 must remain constant. the mcu may write to the 64 locations on a page in any order, which is determined by address lines a5 to a0. as soon as 120 ?ec have expired after the last page write, the internal eeprom storage process begins and the mcu checks programming status. status is checked the same way it is for byte writes, described above. note: be aware that if the upper address bits (a14 to a6) change during page write operations, loss of data may occur. ensure that all bytes for a given page have been successfully stored in the eeprom before proceeding to the next page. correct management of mcu interrupts during eeprom page write operations is essential. 9.1.1.6.3 eeprom software data protect (sdp) the sdp feature is useful for protecting the contents of eeprom from inadvertent write cycles that may occur during uncontrolled mcu bus conditions. these may happen if the application software gets lost or when v cc is not within normal operating range. instructions from the mcu are used to enable and disable sdp mode (see table 9). once enabled, the mcu must write an instruction sequence to eeprom before writing data (much like writing to flash memory). sdp mode can be used for both byte and page writes to eeprom. the device will remain in sdp mode until the mcu issues a valid sdp disable instruction. psd813f devices are shipped with sdp mode disabled. however, within psdsoft, sdp mode may be enabled as part of programming the device with a device programmer (psdpro). the psd813f functional blocks (cont.)
preliminary psd813f family 23 write aah to address 555h write 55h to address aaah write a0h to address 555h page write instruction sdp is set write aah to address 555h write 55h to address aaah write a0h to address 555h write data to be written in any address page write instruction sdp set sdp not set write in memory write data + sdp set after twc (write cycle time) write is enabled sdp enable algorithm figure 3. eeprom sdp enable flowcharts the psd813f functional blocks (cont.) 9.1.1.6.3 eeprom software data protect (sdp) (cont.) to enable sdp mode at run time, the mcu must write three specific data bytes at three specific memory locations, as shown in figure 3. any further writes to eeprom when sdp is set will require this same sequence, followed by the byte(s) to write. the first sdp enable sequence can be followed directly by the byte(s) to be written. to disable sdp mode, the mcu must write specific bytes to six specific locations, as shown in figure 4. the mcu must not be executing code from eeprom when these instructions are invoked. the mcu must be operating from some other memory when enabling or disabling sdp mode. the state of sdp mode is not changed by power on/off sequences (nonvolatile). when either the sdp enable or sdp disable instructions are issued from the mcu, the mcu must use the toggle bit (status bit dq6) or the ready/busy output pin to check programming status. the ready/busy output is driven low from the first write of aah @ 555h until the completion of the internal storage sequence. data polling (status bit dq7) is not supported when issuing the sdp enable or sdp disable commands. note: using the sdp sequence (enabling, disabling, or writing data) is initiated when specific bytes are written to addresses on specific ?ages?of eeprom memory, with no more than 120 ?ec between writes. the addresses 555h and aaah are located on different pages of eeprom. this is how the psd813f distinguishes these instruction sequences from ordinary writes to eeprom, which are expected to be within a single eeprom page.
psd813f family preliminary 24 figure 4. software data protection disable flow chart 9.1.1.6.4 write otp row writing to the otp row (64 bytes) can only be done once per byte, and is enabled by an instruction. this instruction is composed of three specific write operations of data bytes at three specific memory locations followed by the data to be stored in the otp row (refer to table 9). during the write operations, address bit a6 must be zero, while address bits a5-a0 define the otp row byte to be written while any eeprom sector select signal (eesi) is active. writing the otp row is allowed only when sdp mode is not enabled. 9.1.1.7 programming flash memory flash memory must be erased prior to being programmed. the mcu may erase flash memory all at once or by-sector, but not byte-by-byte. a byte of flash memory erases to all logic ones (ff hex), and its bits are programmed to logic zeros. although erasing flash memory occurs on a sector basis, programming flash memory occurs on a byte basis. the psd813f main flash and optional boot flash require the mcu to send an instruction to program a byte or perform an erase function (see table 9). this differs from eeprom, which can be programmed with simple mcu bus write operations (unless eeprom sdp mode is enabled). once the mcu issues a flash memory program or erase instruction, it must check for the status of completion. the embedded algorithms that are invoked inside the psd813f support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or the ready/busy output pin. write aah to address 555h write 55h to address aaah write 80h to address 555h write aah to address 555h write 55h to address aaah write 20h to address 555h page write instruction unprotected state after twc (write cycle time) the psd813f functional blocks (cont.)
preliminary psd813f family 25 the psd813f functional blocks (cont.) 9.1.1.7.1 data polling polling on dq7 is a method of checking whether a program or erase instruction is in progress or has completed. figure 5 shows the data polling algorithm. when the mcu issues a programming instruction, the embedded algorithm within the psd813f begins. the mcu then reads the location of the byte to be programmed in flash to check status. data bit dq7 of this location becomes the compliment of data bit 7of the original data byte to be programmed. the mcu continues to poll this location, comparing dq7 and monitoring the error bit on dq5. when the dq7 matches data bit 7 of the original data, and the error bit at dq5 remains ?? then the embedded algorithm is complete. if the error bit at dq5 is ?? the mcu should test dq7 again since dq7 may have changed simultaneously with dq5 (see figure 5). the error bit at dq5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte or if the mcu attempted to program a ??to a bit that was not erased (not erased is logic ??. it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to flash with the byte that was intended to be written. when using the data polling method after an erase instruction, figure 5 still applies. however, dq7 will be ??until the erase operation is complete. a ??on dq5 will indicate a timeout failure of the erase operation, a ??indicates no error. the mcu can read any location within the sector being erased to get dq7 and dq5. psdsoft will generate ansi c code functions which implement these data polling algorithms. figure 5. data polling flow chart start read dq5 & dq7 at valid address yes yes yes no no no dq7 = data7 dq5 =1 dq7 = data read dq7 fail pass
psd813f family preliminary 26 9.1.1.7.2 data toggle checking the data toggle bit on dq6 is a method of determining whether a program or erase instruction is in progress or has completed. figure 6 shows the data toggle algorithm. when the mcu issues a programming instruction, the embedded algorithm within the psd813f begins. the mcu then reads the location of the byte to be programmed in flash to check status. data bit dq6 of this location will toggle each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this location, checking dq6 and monitoring the error bit on dq5. when dq6 stops toggling (two consecutive reads yield the same value), and the error bit on dq5 remains ?? then the embedded algorithm is complete. if the error bit on dq5 is ?? the mcu should test dq6 again, since dq6 may have changed simultaneously with dq5 (see figure 6). the error bit at dq5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte, or if the mcu attempted to program a ??to a bit that was not erased (not erased is logic ??. it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to flash with the byte that was intended to be written. when using the data toggle method after an erase instructin, figure 6 still applies. dq6 will toggle until the erase operation is complete. a ??on dq5 will indicate a timeout failure of the erase operation, a ??indicates no error. the mcu can read any location within the sector being erased to get dq6 and dq5. psdsoft will generate ansi c code functions which implement these data toggling algorithms. the psd813f functional blocks (cont.) figure 6. data toggle flow chart start read dq5 & dq6 no yes no yes yes no dq6 = toggle dq5 =1 dq6 = toggle read dq6 fail pass
preliminary psd813f family 27 the psd813f functional blocks (cont.) 9.1.1.8 erasing flash memory 9.1.1.8.1. flash bulk erase instruction the flash bulk erase instruction uses six write operations followed by a read operation of the status register, as described in table 9. if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory status. during a bulk erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in section 9.1.1.7. the error bit (dq5) returns a ??if there has been an erase failure (maximum number of erase cycles have been executed). it is not necessary to program the array with 00h because the psd813f will automatically do this before erasing to 0ffh. during execution of the bulk erase instruction, the flash memory will not accept any instructions. 9.1.1.8.2 flash sector erase instruction the sector erase instruction uses six write operations, as described in table 9. additional flash sector erase confirm commands and flash sector addresses can be written subsequently to erase other flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 ?. the input of a new sector erase instruction will restart the time-out period. the status of the internal timer can be monitored through the level of dq3 (erase time-out bit). if dq3 is ?? the sector erase instruction has been received and the timeout is counting. if dq3 is ?? the timeout has expired and the psd813f is busy erasing the flash sector(s). before and during erase timeout, any instruction other than erase suspend and erase resume will abort the instruction and reset the device to read array mode. it is not necessary to program the flash sector with 00h as the psd813f1 will do this automatically before erasing (byte=ffh). during a sector erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in section 9.1.1.7. during execution of the erase instruction, the flash block logic accepts only reset and erase suspend instructions. erasure of one flash sector may be suspended, in order to read data from another flash sector, and then resumed.
psd813f family preliminary 28 the psd813f functional blocks (cont.) 9.1.1.8.3 flash erase suspend instruction when a flash sector erase operation is in progress, the erase suspend instruction will suspend the operation by writing 0b0h to any address when an appropriate chip select (fsi or csbooti) is true. (see table 9). this allows reading of data from another flash sector after the erase operation has been suspended. erase suspend is accepted only during the flash sector erase instruction execution and defaults to read array mode. an erase suspend instruction executed during an erase timeout will, in addition to suspending the erase, terminate the time out. the toggle bit dq6 stops toggling when the psd813f internal logic is suspended. the toggle bit status must be monitored at an address within the flash sector being erased. the toggle bit will stop toggling between 0.1 ? and 15 ? after the erase suspend instruction has been executed. the psd813f will then automatically be set to read flash block memory array mode. if an erase suspend instruction was executed, the following rules apply: attempting to read from a flash sector that was being erased will output invalid data. reading from a flash sector that was not being erased is valid. the flash memory cannot be programmed, and will only respond to erase resume and reset instructions (read is an operation and is ok). if a reset instruction is received, data in the flash sector that was being erased will be invalid. 9.1.1.8.4 flash erase resume instruction if an erase suspend instruction was previously executed, the erase operation may be resumed by this instruction. the erase resume instruction consists of writing 030h to any address while an appropriate chip select (fsi or csbooti) is true. (see table 9.) 9.1.1.9 flash and eeprom memory specific features 9.1.1.9.1 flash and eeprom sector protect each flash and eeprom sector can be separately protected against program and erase functions. sector protection provides additional data security because it disables all program or erase operations. this mode can be activated through the jtag port or a device programmer. sector protection can be selected for each sector using the psdsoft configuration program. this will automatically protect selected sectors when the device is programmed through the jtag port or a device programmer. flash and eeprom sectors can be unprotected to allow updating of their contents using the jtag port or a device programmer. the microcontroller can read (but cannot change) the sector protection bits. any attempt to program or erase a protected flash or eeprom sector will be ignored by the device. the verify operation will result in a read of the protected data. this allows a guarantee of the retention of the protection status. the sector protection status can be read by the mcu through the flash protection and psd/ee protection registers (csiop). see table 11.
preliminary psd813f family 29 the psd813f functional blocks (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot flash protection register 9.1.1.9.2 reset instruction the reset instruction resets the internal memory logic state machine in a few milliseconds. reset is an instruction of either one write operation or three write operations (refer to table 9). 9.1.1.9.3 programming and erasing the boot blocks in psd813f2 and psd813f4 there are two different algorithms for programming and erasing the boot blocks in the psd813f2 and f4 (boot blocks are selected by csbooti). the selection of the correct algorithm is based on the internal die of the psd device, which can be identified based on the flash memory identifier read by the mcu. using the read flash identifier instruction (table 9), the mcu will read one of two ids for the psd813f2 and psd813f4, as shown in table 12. bit definitions: sec_prot 1 = flash or flash boot sector is write protected. sec_prot 0 = flash or flash boot sector is not write protected. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_ *** sec3_prot sec2_prot sec1_prot sec0_prot bit psd/ee protection register bit definitions: sec_prot 1 = eeprom or flash boot sector is write protected. sec_prot 0 = eeprom or flash boot sector is not write protected. security_bit 0 = security bit in device has not been set. 1 = security bit in device has been set. device flash id boot block algorithm psd813f2 and f4 e3h eeprom algorithm (see section 9.1.1.6) psd813f2 and f4 e4h flash algorithm (see section 9.1.1.7) table 12. flash memory id values for psd813f2 and f4 for users of the psd813f2 and f4, the mcu system software must make both algorithms available. within the routine that programs or erases the boot block area, the mcu should use the flash memory identifier first to select the appropriate algorithm. if the identifier is e4h, then it should treat the boot block area as flash memory. if the identifier is e3h, then the mcu should treat the boot block area as eeprom. this will ensure compatibility with all future psd813f2 and f4 devices. note: the mcu must not operate out of main flash while reading the flash memory identifier. it can execute the flash memory identifier command from some other memory, and store the id value for later use. this algorithm selection method only applies to the psd813f2 and f4. the psd813f1 will always use the eeprom algorithm for the boot block area. the psd813f3 and f5 have no boot block area. note that this algorithm selection method is not required when programming or erasing the main flash memory. it only applies to programming or erasing the boot block area. main flash will always require the flash algorithm defined in section 9.1.1.7, regardless of internal die composition. table 11. sector protection/security bit definition *: not used.
psd813f family preliminary 30 the psd813f functional blocks (cont.) 9.1.2 sram the sram is a 16 kbit (2k x 8) memory. the sram is enabled when rs0 the sram chip select output from the dpld is high. rs0 can contain up to two product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to the vstby pin (pc2). if you have an external battery connected to the psd813f, the contents of the sram will be retained in the event of a power loss. the contents of the sram will be retained so long as the battery voltage remains at 2v or greater. if the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs. pin pc4 can be configured as an output that indicates when power is being drawn from the external battery. this vbaton signal will be high with the supply voltage falls below the battery voltage and the battery on pc2 is supplying power to the internal sram. the chip select signal (rs0) for the sram, vstby, and vbaton are all configured using psdsoft configuration. 9.1.3 memory select signals the main flash (fsi), optional eeprom or flash boot (eesi/csbooti), and sram (rs0) memory select signals are all outputs of the dpld. they are setup by writing equations for them in psdabel. the following rules apply to the equations for the internal chip select signals: 1. flash memory and eeprom or flash boot memory sector select signals must not be larger than the physical sector size. 2. any main flash memory sector must not be mapped in the same memory space as another flash sector. 3. an eeprom/flash boot memory sector must not be mapped in the same memory space as another eeprom/flash boot sector. 4. sram, i/o, and peripheral i/o spaces must not overlap. 5. an eeprom/flash boot memory sector may overlap a main flash memory sector. in case of overlap, priority will be given to the eeprom/flash boot sector. 6. sram, i/o, and peripheral i/o spaces may overlap any other memory sector. priority will be given to the sram, i/o, or peripheral i/o. example fs0 is valid when the address is in the range of 8000h to bfffh, ees0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 will always access the sram. any address in the range of ees0 greater than 87ffh (and less than 9fffh) will automatically address eeprom memory segment 0. any address greater than 9fffh will access the flash memory segment 0. you can see that half of the flash memory segment 0 and one-fourth of eeprom segment 0 can not be accessed in this example. also note that an equation that defined fs1 to anywhere in the range of 8000h to bfffh would not be valid. figure 7 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest.
preliminary psd813f family 31 the psd813f functional blocks (cont.) level 1 sram, i /o, or peripheral i /o level 2 eeprom / flash boot memory highest priority lowest priority level 3 flash memory figure 7. priority level of memory and i/o components 9.1.3.1. memory select configuration for mcus with separate program and data spaces the 8031 and compatible family of microcontrollers, which includes the 80c51, 80c151, 80c251, and 80c51xa, have separate address spaces for code memory (selected using psen) and data memory (selected using rd). any of the memories within the psd813f can reside in either space or both spaces. this is controlled through manipulation of the vm register that resides in the psds csiop space. the vm register is set using psdsoft to have an initial value. it can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. for example, i may wish to have sram and flash in data space at boot, and eeprom in program space at boot, and later swap eeprom and flash. this is easily done with the vm register by using psdsoft configuration to configure it for boot up and having the microcontroller change it when desired. table 13 describes the vm register. bit 7 bit 6* bit 5* bit 4 bit 3 bit 2 bit 1 bit 0 pio_en fl_data ee_data fl_code ee_code sram_code 0 = disable ** 0 = rd 0 = rd 0 = psen 0 = psen 0 = psen pio mode can? can? can? can? can? access access access access access flash eeprom/ flash eeprom/ sram boot flash boot flash 1= enable ** 1 = rd 1 = rd 1 = psen 1 = psen 1 = psen pio mode access access access access access flash eeprom/ flash eeprom/ sram boot flash boot flash table 13. vm register note: bits 6-5 are not used.
psd813f family preliminary 32 the psd813f functional blocks (cont.) 9.1.3.2 configuration modes for mcus with separate program and data spaces 9.1.3.2.1 separate space modes code memory space is separated from data memory space. for example, the psen signal is used to access the program code from the flash memory, while the rd signal is used to access data from the eeprom, sram and i/o ports. this configuration requires the vm register to be set to 0ch. 9.1.3.2.2 . combined space modes the program and data memory spaces are combined into one space that allows the main flash memory, eeprom, and sram to be accessed by either psen or rd. for example, to configure the main flash memory in combined space mode, bits 2 and 4 of the vm register are set to 1. 9.1.3.2.3 mixed modes this allows individual flash memory or eeprom sectors with overlapping addresses to be configured in either data space or program space. flash memory or eeprom sector select signals must be qualified with the rd or psen input in the fs0-fs7 or ees0-ees3 equations. an active rd or psen will select memory sectors in the data space or in the program space. for memory sectors that reside in data space or program space, the access time is calculated from rd or psen valid to data valid. 9.1.3.5 80c31 memory map example in this example, the psd memory will be configured as shown in figure 8.
preliminary psd813f family 33 the psd813f functional blocks (cont.) flash memory sectors fs0-1 program space eeprom sectors ees0-1 ffffh 8000h 4000h 0 flash memory sectors fs0-1 data space sram eeprom sectors ees2-3 ffffh 8000h 47ffh 4000h 0 figure 8. 80c31 memory map example o flash memory sectors fs0-1 will be mapped from 8000-ffffh in the combined space mode (in both program space and data space). bits 2 and 4 of the vm register are set to 1. o eeprom sectors ees0-1 will be mapped in the program space from 0000h-3fffh. eeprom sectors ees2-3 will be mapped in the data space from 0000h-3fffh. bits 1 and 3 of the vm register are set to 1. o sram will be mapped in the data space from 4000-47ffh. bit 0 of the vm register is set to 0. the abel equations in psdsoft will be as followed: fs0 = (address>= ^h8000) & (address<=^hbfff); fs1 = (address>= ^hc000) & (address<=^hffff); ees0 = (address>= ^h0000) & (address<=^h1fff) & !psen; ees1 = (address>= ^h2000) & (address<=^h3fff) & !psen; ees2 = (address>= ^h0000) & (address<=^h1fff) & psen; ees3 = (address>= ^h2000) & (address<=^h3fff) & psen; rs0 = (address>= ^h4000) & (address<=^h47ff); bit 7 bit 6* bit 5* bit 4 bit 3 bit 2 bit 1 bit 0 pio_en rd_en psen_en 0 = disable ** 1 = rd 1 = rd 1 = psen 1 = psen 0 = psen pio mode can can can can can not access access access access access flash eeprom/ flash eeprom/ sram boot flash boot flash table 14. vm register contents in the 80c31 memory map example when the microcontroller reads the vm register, the contents read back are shown in table 14. the vm register content at power up is specified in psdsoft. note: bits 6-5 are not used.
psd813f family preliminary 34 the psd813f functional blocks (cont.) flash dpld eeprom sram rs0 ees0-3 fs0-7 cs cs cs oe oe rd psen oe figure 9. 8031 memory modes ?separate space mode flash dpld eeprom sram rs0 ees0-3 fs0-7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe figure 10. 80c31 memory mode ?combined space mode
preliminary psd813f family 35 reset d0-d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 flash dpld and flash cpld internal selects and logic flash pld pgr4 pgr5 pgr6 pgr7 figure 11. page register the psd813f functional blocks (cont.) 9.1.4 page register the eight bit page register increases the addressing capability of the microcontroller by a factor of up to 256. the contents of the register can also be read by the microcontroller. the outputs of the page register (pgr0-pgr7) are inputs to the dpld decoder and can be included in the flash memory, eeprom, and sram chip select equations. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the cpld for general logic. see application note 57. figure 11 shows the page register. the eight flip flops in the register are connected to the internal data bus d0-d7. the microcontroller can write to or read from the page register. the page register can be accessed at address location csiop + e0h.
psd813f family preliminary 36 the psd813f functional blocks (cont.) 9.2 plds the plds bring programmable logic functionality to the psd813f. after specifying the logic for the plds using the psdabel tool in psdsoft, the logic is programmed into the device and available upon power-up. the psd813f contains two plds: the decode pld (dpld), and the complex pld (cpld). the plds are briefly discussed in the next few paragraphs, and in more detail in sections 9.2.1 and 9.2.2. figure 12 shows the configuration of the plds. the dpld performs address decoding for internal and external components, such as memory, registers, and i/o port selects. the cpld can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. these logic functions can be constructed using the 16 output micro ? cells (omcs), 24 input micro ? cells (imcs), and the and array. the cpld can also be used to generate external chip selects. the and array is used to form product terms. these product terms are specified using psdabel. an input bus consisting of 73 signals is connected to the plds. the signals are shown in table 15. input source input name number of signals mcu address bus a[15:0] * 16 mcu control signals cntl[2:0] 3 reset rst 1 power down pdn 1 port a input micro ? cells pa[7-0] 8 port b input micro ? cells pb[7-0] 8 port c input micro ? cells pc[7-0] 8 port d inputs pd[2:0] 3 page register pgr(7:0) 8 micro ? cell ab feedback mcellab.fb[7:0] 8 micro ? cell bc feedback mcellbc.fb[7:0] 8 eeprom/boot flash programming status bit rdy/bsy 1 table 15. dpld and cpld inputs note: the address inputs are a[19:4] in 80c51xa mode. the turbo bit in zpsd813f the plds in the zpsd813f can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70 ns. setting the turbo mode bit to off (bit 3 of the pmmr0 register) automatically places the plds into standby if no inputs are changing. turbo-off mode increases propagation delays while reducing power consumption. refer to the power management unit section on how to set the turbo bit. additionally, five bits are available in the pmmr2 register to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations.
preliminary psd813f family 37 pld input bus 8 input micro ? cell & input ports direct micro ? cell input to mcu data bus csiop select sram select flash eeprom selects (psd813f1) or flash boot memory selects (psd813f2) decode pld page register peripheral selects jtag select cpld pt alloc. micro ? cell alloc. mcellab mcellbc direct micro ? cell access from mcu data bus 24 input micro ? cell (port a,b,c) 16 output micro ? cell i/o ports flash memory selects 3 port d inputs to port a or b to port b or c data bus 8 8 8 4 1 1 2 1 external chip selects to port d 3 73 16 73 24 output micro ? cell feedback figure 12. pld block diagram
psd813f family preliminary 38 the psd813f functional blocks (cont.) each of the two plds has unique characteristics suited for its applications they are described in the following sections. 9.2.1 decode pld (dpld) the dpld, shown in figure 13, is used for decoding the address for internal and external components. the dpld can generate the following decode signals: 8 sector selects for the main flash memory (three product terms each) 4 sector selects for the optional eeprom or flash boot memory (three product terms each) 1 internal sram select signal (two product terms) 1 internal csiop (psd configuration register) select signal 1 jtag select signal (enables jtag on port c) 2 internal peripheral select signals (peripheral i/o mode). 9.2.2 complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. the cpld can also be used to generate 3 external chip selects, routed to port d. although external chip selects can be produced by any output micro ? cell, these three external chip selects on port d do not consume any output micro ? cells. as shown in figure 12, the cpld has the following blocks: 24 input micro ? cells (imcs) 16 output micro ? cells (omcs) micro ? cell allocator product term allocator and array capable of generating up to 137 product terms four i/o ports. each of the blocks are described in the subsections that follow. the input and output micro ? cells are connected to the psd813f internal data bus and can be directly accessed by the microcontroller. this enables the mcu software to load data into the output micro ? cells or read data from both the input and output micro ? cells. this feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the and logic array as required in most standard pld macrocell architectures.
preliminary psd813f family 39 (inputs) (24) (8) (16) (1) pdn (apd output) i /o ports (port a,b,c) (8) pgr0 - pgr7 (8) mcellab.fb [7:0] (feedbacks) mcellbc.fb [7:0] (feedbacks) a [ 15:0 ] * (3) (3) pd [ 2:0 ] (ale,clkin,csi) cntrl [ 2:0 ] ( read/write control signals) (1) (1) reset rd_bsy rs0 csiop psel0 psel1 8 flash memory sector selects sram select i/o decoder select peripheral i/o mode select ees0 or csboot 0 ees1 or csboot 1 ees2 or csboot 2 ees3 or csboot 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 2 jtagsel figure 13. dpld logic array * note: the address inputs are a[19:4] in 80c51xa mode.
psd813f family preliminary 40 i/o ports cpld micro ? cells input micro ? cells latched address out mux mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other micro ? cells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) micro ? cell feedback i/o port input ale/as pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select micro ? cell to i/o port alloc. fgpld output to other i/o ports pld input bus pld input bus mcu address / data bus micro ? cell out to mcu data load control and array fgpld output i/o pin figure 14. the micro ? cell and i/o port
preliminary psd813f family 41 the psd813f functional blocks (cont.) 9.2.2.1 output micro ? cell eight of the output micro ? cells are connected to ports a and b pins and are named as mcellab0-7. the other eight micro ? cells are connected to ports b and c pins and are named as mcellbc0-7. if an mcellab output is not assigned to a specific pin in psdabel, the micro ? cell allocator will assign it to either port a or b. the same is true for a mcellbc output on port b or c. table 16 shows the micro ? cells and port assignment. maximum native borrowed data bit for output port product product loading or micro ? cell assignment terms terms reading mcellab0 port a0, b0 3 6 d0 mcellab1 port a1, b1 3 6 d1 mcellab2 port a2, b2 3 6 d2 mcellab3 port a3, b3 3 6 d3 mcellab4 port a4, b4 3 6 d4 mcellab5 port a5, b5 3 6 d5 mcellab6 port a6, b6 3 6 d6 mcellab7 port a7, b7 3 6 d7 mcellbc0 port b0, c0 4 5 d0 mcellbc1 port b1, c1 4 5 d1 mcellbc2 port b2, c2 4 5 d2 mcellbc3 port b3, c3 4 5 d3 mcellbc4 port b4, c4 4 6 d4 mcellbc5 port b5, c5 4 6 d5 mcellbc6 port b6, c6 4 6 d6 mcellbc7 port b7, c7 4 6 d7 table 16. output micro ? cell port and data bit assignments the output micro ? cell (omc) architecture is shown in figure 15. as shown in the figure, there are native product terms available from the and array, and borrowed product terms available (if unused) from other omcs. the polarity of the product term is controlled by the xor gate. the omc can implement either sequential logic, using the flip-flop element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the omc can be configured as a d, t, jk, or sr type in the psdabel program. the flip-flops clock, preset, and clear inputs may be driven from a product term of the and array. alternatively, the external clkin signal can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of the clock input. the preset and clear are active-high inputs. each clear input can use up to two product terms.
psd813f family preliminary 42 9.2.2.2 the product term allocator the cpld has a product term allocator. the psdabel compiler uses the allocator to borrow and place product terms from one micro ? cell to another. the following list summarizes how product terms are allocated: mcellab0-7 all have three native product terms and may borrow up to six more mcellbc0-3 all have four native product terms and may borrow up to five more mcellbc4-7 all have four native product terms and may borrow up to six more. each micro ? cell may only borrow product terms from certain other micro ? cells. product terms already in use by one micro ? cell will not be available for a different micro ? cell. if an equation requires more product terms than what is available to it, then ?xternal product terms will be required, which will consume other omcs. if external product terms are used, extra delay will be added for the equation that required the extra product terms. this is called product term expansion. psdsoft will perform this expansion as needed. 9.2.2.3 loading and reading the output micro ? cells (omcs) the omcs occupy a memory location in the mcu address space, as defined by the csiop (refer to the i/o section). the flip-flops in each of the 16 omcs can be loaded from the data bus by a microcontroller. loading the omcs with data from the mcu takes priority over internal functions. as such, the preset, clear, and clock inputs to the flip-flop can be overridden by the mcu. the ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. data can be loaded to the omcs on the trailing edge of the wr signal (edge loading) or during the time that the wr signal is active (level loading). the method of loading is specified in psdsoft configuration. 9.2.2.4 the omc mask register there is one mask register for each of the two groups of eight omcs. the mask registers can be used to block the loading of data to individual omcs. the default value for the mask registers is 00h, which allows loading of the omcs. when a given bit in a mask register is set to a ?? the mcu will be blocked from writing to the associated omc. for example, suppose mcellab0-3 are being used for a state machine. you would not want a mcu write to mcellab to overwrite the state machine registers. therefore, you would want to load the mask register for mcellab (mask micro ? cell ab) with the value 0fh. 9.2.2.5 the output enable of the omc the omc can be connected to an i/o port pin as a pld output. the output enable of each port pin driver is controlled by a single product term from the and array, ored with the direction register output. the pin is enabled upon power up if no output enable equation is defined and if the pin is declared as a pld output in psdsoft. if the omc output is declared as an internal node and not as a port pin output in the psdabel file, then the port pin can be used for other i/o functions. the internal node feedback can be routed as an input to the and array. the psd813f functional blocks (cont.)
preliminary psd813f family 43 pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input micro ? cell i/o pin micro ? cell allocator internal data bus d [ 7:0 ] direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd micro ? cell cs figure 15. cpld output micro ? cell the psd813f functional blocks (cont.)
psd813f family preliminary 44 9.2.2.6 input micro ? cells (imcs) the cpld has 24 imcs, one for each pin on ports a, b, and c. the architecture of the imc is shown in figure 16. the imcs are individually configurable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the pld input bus. the outputs of the imcs can be read by the microcontroller through the internal data bus. the enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the cpld and array or the mcu address strobe (ale/as). each product term output is used to latch or clock four imcs. port inputs 3-0 can be controlled by one product term and 7-4 by another. configurations for the imcs are specified by equations written in psdabel (see application note 55). outputs of the imcs can be read by the mcu via the imc buffer. see the i/o port section on how to read the imcs. imcs can use the address strobe to latch address bits higher than a15. any latched addresses are routed to the plds as inputs. imcs are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. figure 17 shows a typical configuration where the master mcu writes to the port a data out register. this, in turn, can be read by the slave mcu via the activation of the ?lave-read?output enable product term. the slave can also write to the port a imcs and the master can then read the imcs directly. note that the ?lave-read?and ?lave-wr?signals are product terms that are derived from the slave mcu inputs rd, wr, and slave_cs. the psd813f functional blocks (cont.)
preliminary psd813f family 45 output micro ? cells bc and micro ? cell ab pt pt feedback and array pld input bus port driver i/o pin internal data bus d [ 7: 0 ] direction register mux mux ale/as pt q q d d g latch input micro ? cell enable ( .oe ) d ff input micro ? cell _ rd figure 16. input micro ? cell the psd813f functional blocks (cont.)
psd813f family preliminary 46 master mcu mcu-rd mcu-rd mcu-wr slave wr slave cs mcu-wr d [ 7:0 ] d [ 7:0 ] cpld dq qd port a data out register port a input micro ? cell port a slave read slave mcu rd wr psd813f figure 17. handshaking communication using input micro ? cells the psd813f functional blocks (cont.)
preliminary psd813f family 47 the psd813f functional blocks (cont.) 9.3 microcontroller bus interface the ?o-glue logic?psd813f microcontroller bus interface can be directly connected to most popular microcontrollers and their control signals. key 8-bit microcontrollers with their bus types and control signals are shown in table 17. the interface type is specified using the psdsoft configuration. data bus mcu width cntl0 cntl1 cntl2 pc7 pd0** adio0 pa3-pa0 pa7-pa3 8031 8 wr rd psen * ale a0 ** 80c51xa 8 wr rd psen * ale a4 a3-a0 * 80c251 8 wr psen ** ale a0 ** 80c251 8 wr rd psen * ale a0 ** 80198 8 wr rd ** ale a0 ** 68hc11 8 r/w e ** as a0 ** 68hc912 8 r/w e * dbe as a0 ** z80 8 wr rd *** a0 d3-d0 d7-d4 neuron 3150 chip 8 r/w e *** a0 d3-d0 d7-d4 z8 8 r/w ds ** as a0 ** 68330 8 r/w ds ** as a0 ** m37702m2 8 r/w e ** ale a0 d3-d0 d7-d4 table 17. microcontrollers and their control signals * * unused cntl2 pin can be configured as cpld input. other unused pins (pc7, pd0, pa3-0) can be ** configured for other i/o functions. ** ale/as input is optional for microcontrollers with a non-multiplexed bus 9.3.1. interfacing 16-bit mcus with two psd813f devices. the psd813f has an internal 8-bit data bus. users of 16-bit data bus mcus can connect two psd813f devices in parallel such that one is tied to the upper data byte (d15-d8) and the other is connected to the lower data byte (d7-d0). refer to psd813f application notes on the configuration of two psd813f to 16-bit mcus. 9.3.2. psd813f interface to a multiplexed 8-bit bus figure 18 shows an example of a system using a microcontroller with an 8-bit multiplexed bus and a psd813f. the adio port on the psd813f is connected directly to the microcontroller address/data bus. ale latches the address lines internally. latched addresses can be brought out to port a or b. the psd813f drives the adio data bus only when one of its internal resources is accessed and the rd input is active. should the system address bus exceed sixteen bits, ports a, b, c, or d may be used as additional address inputs. 9.3.3. psd813f interface to a non-multiplexed 8-bit bus figure 19 shows an example of a system using a microcontroller with an 8-bit non-multiplexed bus and a psd813f. the address bus is connected to the adio port, and the data bus is connected to port a. port a is in tri-state mode when the psd813f is not accessed by the microcontroller. should the system address bus exceed sixteen bits, ports b, c, or d may be used for additional address inputs.
psd813f family preliminary 48 the psd813f functional blocks (cont.) micro - controller wr rd bhe ale reset ad [ 7:0 ] a [ 15:8 ] a [ 15: 8 ] a [ 7: 0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) psd813f figure 18. an example of a typical 8-bit multiplexed bus interface
preliminary psd813f family 49 the psd813f functional blocks (cont.) micro - controller wr rd bhe ale reset d [ 7:0 ] a [ 15:0 ] a [ 23:16 ] d [ 7:0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d (optional) psd813f figure 19. an example of a typical 8-bit non-multiplexed bus interface
psd813f family preliminary 50 the psd813f functional blocks (cont.) 9.3.4 data byte enable reference microcontrollers have different data byte orientations. the following table shows how the psd813f interprets byte/word operations in different bus write configurations. even-byte refers to locations with address a0 equal to zero and odd byte as locations with a0 equal to one. bhe a0 d7-d0 x 0 even byte x 1 odd byte table 18. eight-bit data bus 9.3.5 microcontroller interface examples figures 20 through 24 show examples of the basic connections between the psd813f and some popular microcontrollers. the psd813f control input pins are labeled as to the microcontroller function for which they are configured. the mcu interface is specified using the psdsoft configuration. 9.3.5.1 80c31 figure 20 shows the interface to the 80c31, which has an 8-bit multiplexed address/data bus. the lower address byte is multiplexed with the data bus. the microcontroller control signals psen, rd, and wr may be used for accessing the internal memory components and i/o ports. the ale input (pin pd0) latches the address. 9.3.5.2 80c251 the intel 80c251 microcontroller features a user-configurable bus interface with four possible bus configurations, as shown in table 19. configuration 1 is 80c31 compatible, and the bus interface to the psd813f is identical to that shown in figure 20. configurations 2 and 3 have the same bus connection as shown in figure 21. there is only one read input (psen) connected to the cntl1 pin on the psd813f. the a16 connection to the pa0 pin allows for a larger address input to the psd813f. configuration 4 is shown in figure 22. the rd signal is connected to cntl1 and the psen signal is connected to the cntl2. the 80c251 has two major operating modes: page mode and non-page mode. in non-page mode, the data is multiplexed with the lower address byte, and ale is active in every bus cycle. in page mode, data d[7:0] is multiplexed with address a[15:8]. in a bus cycle where there is a page hit, the ale signal is not active and only addresses a[7:0] are changing. the psd813f supports both modes. in page mode, the psd bus timing is identical to non-page mode except the address hold time and setup time with respect to ale is not required. the psd access time is measured from address a[7:0] valid to data in valid.
preliminary psd813f family 51 the psd813f functional blocks (cont.) configuration 80c251 connecting to page mode read/write psd813f pins pins wr cntl0 non-page mode, 80c31 compatible 1 rd cntl1 a [ 7:0 ] multiplex with d [ 7:0 } psen cntl2 2 wr cntl0 non-page mode psen only cntl1 a [ 7:0 ] multiplex with d [ 7:0 } 3 wr cntl0 page mode psen only cntl1 a [ 15:8 ] multiplex with d [ 7:0 } 4 wr cntl0 page mode rd cntl1 a [ 15:8 ] multiplex with d [ 7:0 } psen cntl2 table 19. 80c251 configurations 9.3.5.3 80c51xa the philips 80c51xa microcontroller family supports an 8- or 16-bit multiplexed bus that can have burst cycles. address bits a[3:0] are not multiplexed, while a[19:4] are multiplexed with data bits d[15:0] in 16-bit mode. in 8-bit mode, a[11:4] are multiplexed with data bits d[7:0]. the 80c51xa can be configured to operate in eight-bit data mode. (shown in figure 23). the 80c51xa improves bus throughput and performance by executing burst cycles for code fetches. in burst mode, address a19-4 are latched internally by the psd813f, while the 80c51xa changes the a3-0 lines to fetch up to 16 bytes of code. the psd access time is then measured from address a3-a0 valid to data in valid. the psd bus timing requirement in burst mode is identical to the normal bus cycle, except the address setup and hold time with respect to ale does not apply. 9.3.5.4 68hc11 figure 24 shows an interface to a 68hc11 where the psd813f1 is configured in 8-bit multiplexed mode with e and r/w settings. the dpld can generate the read and wr signals for external devices.
psd813f family preliminary 52 ea/vp x1 x2 reset reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd0-ale pd1 pd2 reset rd wr psen ale/p txd rxd reset 29 28 27 25 24 23 22 21 30 39 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 38 37 36 35 34 33 32 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 50 49 10 9 8 7 6 5 4 3 2 52 51 psd813f 80c31 ad [ 7:0 ] ad [ 7:0 ] 21 22 23 24 25 26 27 28 17 16 29 30 a8 a9 a10 a11 a12 a13 a14 a15 rd wr psen ale 11 10 reset 20 19 18 17 14 13 12 11 figure 20. interfacing the psd813f with an 80c31 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr a16 rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/rxd p3.1/txd p3.2/int0 x2 x1 p3.3/int1 rst ea a16 * a17 * a17 p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd/a16 pc0 pc1 pc3 pc4 pc5 pc6 pc7 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb psd813f reset reset 35 p3.4/t0 p3.5/t1 16 15 17 10 reset pc2 figure 21. interfacing the psd813f to the 80c251, with one read input * *connection is optional. **non-page mode: ad[7:0] - adio[7:0].
preliminary psd813f family 53 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr psen rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/rxd p3.1/txd p3.2/int0 x2 x1 p3.3/int1 rst ea p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd/a16 pc0 pc1 pc3 pc4 pc5 pc6 pc7 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb psd813f reset reset 35 p3.4/t0 p3.5/t1 16 15 17 10 reset pc2 figure 22. interfacing the psd813f to the 80c251, with read and psen inputs adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2 (psen) pd0-ale pd1 pd2 reset 31 33 36 2 3 4 5 43 42 41 40 39 38 37 24 25 26 27 28 29 30 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a13 a14 a18 a19 a17 a15 a16 a0 a1 a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a16 a17 a18 a19 a15 a13 a14 txd1 t2ex t2 t0 rst ea/wait busw a1 a0/wrh a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 psen rd wrl pc0 pc1 pc3 pc4 pc5 pc6 pc7 ale psen rd wr ale 32 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 7 9 8 16 xtal1 xtal2 rxd0 txd0 rxd1 21 20 11 13 6 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 a0 a1 a2 a3 80c51xa psd813f reset reset 35 17 int0 int1 14 10 15 pc2 figure 23. interfacing the psd813f to the 80c51xa, 8-bit data bus
psd813f family preliminary 54 9 10 11 12 13 14 15 16 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 (r _ w) cntl1(e) cntl 2 pd0 as pd1 pd2 reset 20 21 22 23 24 25 3 5 4 6 42 41 40 39 38 37 36 35 ad0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a14 a15 a13 a11 a12 ad1 ad2 ad3 ad4 ad5 ad6 ad7 e as r/w xt ex reset irq xirq pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc0 pc1 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r/w 31 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 8 7 17 19 18 34 33 32 43 44 45 46 47 48 49 50 52 51 30 29 28 27 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 7 6 5 4 3 2 52 51 modb 2 68hc11 psd813f reset reset ad[7:0] ad[7:0] pc2 figure 24. interfacing the psd813f with a 68hc11
preliminary psd813f family 55 the psd813f functional blocks (cont.) 9.4 i/o ports there are four programmable i/o ports: ports a, b, c, and d. each of the ports is eight bits except port d, which is 3 bits. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft configuration or by the microcontroller writing to on-chip registers in the csiop address space. the topics discussed in this section are: general port architecture port operating modes port configuration registers port data registers individual port functionality. 9.4.1 general port architecture the general architecture of the i/o port is shown in figure 25. individual port architectures are shown in figures 27 through 30. in general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. exceptions will be noted. as shown in figure 25, the ports contain an output multiplexer whose selects are driven by the configuration bits in the control registers (ports a and b only) and psdsoft configuration. inputs to the multiplexer include the following: o output data from the data out register o latched address outputs o cpld micro ? cell output o external chip select from cpld. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the pdb is connected to the internal data bus for feedback and can be read by the microcontroller. the data out and micro ? cell outputs, direction and control registers, and port pin input are all connected to the pdb. the port pins tri-state output driver enable is controlled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in the psdabel file, then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the microcontroller. the pdb feedback path allows the microcontroller to check the contents of the registers. ports a, b, and c have embedded input micro ? cells (imcs). the imcs can be configured as latches, registers, or direct inputs to the plds. the latches and registers are clocked by the address strobe (as/ale) or a product term from the pld and array. the outputs from the imcs drive the pld input bus and can be read by the microcontroller. refer to the imc subsection of the pld section.
psd813f family preliminary 56 internal data bus data out reg. dq d g q dq dq wr wr wr address micro ? cell outputs enable product term ( .oe ) ext cs ale read mux p d b cpld - input control reg. dir reg. input micro ? cell enable out data in output select output mux port pin data out address figure 25. general i/o port architecture the psd813f functional blocks (cont.)
preliminary psd813f family 57 the psd813f functional blocks (cont.) 9.4.2 port operating modes the i/o ports have several modes of operation. some modes can be defined using psdabel, some by the microcontroller writing to the control registers in csiop space, and some by both. the modes that can only be defined using psdsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the microcontroller can be done so dynamically at run-time. the pld i/o, data port, address input, and peripheral i/o modes are the only modes that must be defined before programming the device. all other modes can be changed by the microcontroller at run-time. see application note 55 for more detail. table 20 summarizes which modes are available on each port. table 23 shows how and where the different modes are configured. each of the port operating modes are described in the following subsections. port mode port a port b port c port d mcu i/o yes yes yes yes pld i/o mcellab outputs yes yes no no mcellbc outputs no yes yes no additional ext. cs outputs no no no yes pld inputs yes yes yes yes address out yes (a7 0) yes (a7 0) no no or a15 8) address in yes yes yes yes data port yes (d7 0) no no no peripheral i/o yes no no no jtag isp no no yes * no table 20. port operating modes * can be multiplexed with other i/o functions.
psd813f family preliminary 58 the psd813f functional blocks (cont.) control direction vm defined in defined in register register register jtag mode psdabel psdconfiguration setting setting setting enable declare 1 = output, mcu i/o pins only na* 0 0 = input na na (note 1) pld i/o logic na na (note 1) na na equations data port na specify bus type na na na na (port a) address out declare na 1 1 (note 1) na na (port a,b) pins only address in logic equation (port a,b,c,d) for input na na na na na micro ? cells peripheral i/o logic equations na na na pio bit = 1 na (port a) (psel0 & 1) jtag isp jtagsel jtag configuration na na na jtag_ (note 2) enable table 21. port operating mode settings * na = not applicable note: 1. the direction of the port a,b,c, and d pins are controlled by the direction register ored with the individual output enable product term (.oe) from the cpld and array. 2. any of these three methods will enable jtag pins on port c. 9.4.2.1 mcu i/o mode in the mcu i/o mode, the microcontroller uses the psd813f ports to expand its own i/o ports. by setting up the csiop space, the ports on the psd813f are mapped into the microcontroller address space. the addresses of the ports are listed in table 7. a port pin can be put into mcu i/o mode by writing a ??to the corresponding bit in the control register. the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output enable product term. see the subsection on the direction register in the ?ort registers?section. when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the microcontroller can read the port input through the data in buffer. see figure 25. ports c and d do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if equation are written for them in psdabel. 9.4.2.2 pld i/o mode the pld i/o mode uses a port as an input to the cplds input micro ? cells, and/or as an output from the cplds output micro ? cells. the output can be tri-stated with a control signal. this output enable control signal can be defined by a product term from the pld, or by setting the corresponding bit in the direction register to ?? the corresponding bit in the direction register must not be set to ??if the pin is defined as a pld input pin in psdabel. the pld i/o mode is specified in psdabel by declaring the port pins, and then writing an equation assigning the pld i/o to a port.
preliminary psd813f family 59 the psd813f functional blocks (cont.) 9.4.2.4 address in mode for microcontrollers that have more than 16 address lines, the higher addresses can be connected to port a, b, c, and d. the address input can be latched in the input micro ? cell by the address strobe (ale/as). any input that is included in the dpld equations for the plds flash, eeprom, or sram is considered to be an address input. 9.4.2.5 data port mode port a can be used as a data bus port for a microcontroller with a non-multiplexed address/data bus. the data port is connected to the data bus of the microcontroller. the general i/o functions are disabled in port a if the port is configured as a data port. 9.4.2.6 peripheral i/o mode peripheral i/o mode can be used to interface with external peripherals. in this mode, all of port a serves as a tri-stateable, bi-directional data buffer for the microcontroller. peripheral i/o mode is enabled by setting bit 7 of the vm register to a ?? figure 26 shows how port a acts as a bi-directional buffer for the microcontroller data bus if peripheral i/o mode is enabled. an equation for psel0 and/or psel1 must be written in psdabel. the buffer is tri-stated when psel 0 or 1 is not active. 9.4.2.7 jtag isp port c is jtag compliant, and can be used for in-system programming (isp). you can multiplex jtag operations with other functions on port c because isp is not performed during normal system operation. for more information on the jtag port, refer to section 9.6. 9.4.2.3 address out mode for microcontrollers with a multiplexed address/data bus, address out mode can be used to drive latched addresses onto the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direction register and control register must be set to a ??for pins to use address out mode. this must be done by the mcu at run-time. see table 22 for the address output pin assignments on ports a and b for various mcus. for non-multiplexed 8 bit bus mode, address lines a[7:0] are available to port b in address out mode. note: do not drive address lines with address out mode to an external memory device if it is intended for the mcu to boot from the external device. the mcu must first boot from psd memory so the direction and control register bits can be set. microcontroller port a (3:0) port a (7:4) port b (3:0) port b (7:4) 8051xa (8-bit) n/a* address (7:4) address (11:8) n/a 80c251 n/a n/a address (11:8) address (15:12) (page mode) all other address (3:0) address (7:4) address (3:0) address (7:4) 8-bit multiplexed 8-bit n/a n/a address [3:0] address [7:4] non-multiplexed bus table 22. i/o port latched address output assignments n/a = not applicable.
psd813f family preliminary 60 the psd813f functional blocks (cont.) rd psel0 psel1 psel vm register bit 7 wr pa0 - pa7 d0-d7 data bus figure 26. peripheral i/o mode 9.4.3 port configuration registers (pcrs) each port has a set of pcrs used for configuration. the contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses given in table 7. the addresses in table 7 are the offsets in hex from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three pcrs, shown in table 23, are used for setting the port configurations. the default power-up state for each register in table 23 is 00h. register name port mcu access control a,b write/read direction a,b,c,d write/read drive select* a,b,c,d write/read table 23. port configuration registers * note: see table 27 for drive register bit definition.
preliminary psd813f family 61 the psd813f functional blocks (cont.) 9.4.3.1 control register any bit set to ??in the control register sets the corresponding port pin to mcu i/o mode, and a ??sets it to address out mode. the default mode is mcu i/o. only ports a and b have an associated control register. 9.4.3.2 direction register the direction register, in conjunction with the output enable (except for port d), controls the direction of data flow in the i/o ports. any bit set to ??in the direction register will cause the corresponding pin to be an output, and any bit set to ??will cause it to be an input. the default mode for all port pins is input. figures 27 and 29 show the port architecture diagrams for ports a/b and c, respectively. the direction of data flow for ports a, b, and c are controlled not only by the direction register, but also by the output enable product term from the pld and array. if the output enable product term is not active, the direction register has sole control of a given pins direction. an example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in table 26. since port d only contains three pins, the direction register for port d has only the three least significant bits active. direction register bit port pin mode 0 input 1 output table 24. port pin direction control, output enable p.t. not defined direction register bit output enable p.t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output table 25. port pin direction control, output enable p.t. defined bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0000 111 table 26. port direction assignment example
psd813f family preliminary 62 drive bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register port a open open open open slew slew slew slew drain drain drain drain rate rate rate rate port b open open open open slew slew slew slew drain drain drain drain rate rate rate rate port c open open open open open open open open drain drain drain drain drain drain drain drain port d na na na na na slew slew slew rate rate rate table 27. drive register pin assignment note: na = not applicable. the psd813f functional blocks (cont.) 9.4.3.3 drive select register the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corresponding bit in the drive select register is set to a ?? the default pin drive is cmos. aside: the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive register is set to ?? the default rate is slow slew. table 27 shows the drive register for ports a, b, c, and d. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for.
preliminary psd813f family 63 the psd813f functional blocks (cont.) 9.4.4 port data registers the port data registers, shown in table 28, are used by the microcontroller to write data to or read data from the ports. table 28 shows the register name, the ports having each register type, and microcontroller access for each register type. the registers are described below. 9.4.4.1 data in port pins are connected directly to the data in buffer. in mcu i/o input mode, the pin input is read through the data in buffer. 9.4.4.2 data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are driven out to the pins if the direction register or the output enable product term is set to ?? the contents of the register can also be read back by the microcontroller. 9.4.4.3 output micro ? cells (omcs) the cpld omcs occupy a location in the microcontrollers address space. the microcontroller can read the output of the omcs. if the mask micro ? cell register bits are not set, writing to the micro ? cell loads data to the micro ? cell flip flops. refer to the pld section for more details. 9.4.4.4 mask micro ? cell register each mask register bit corresponds to an omc flip flop. when the mask register bit is set to a ?? loading data into the omc flip flop is blocked. the default value is ??or unblocked. 9.4.4.5 input micro ? cells (imcs) the imcs can be used to latch or store external inputs. the outputs of the imcs are routed to the pld input bus, and can be read by the microcontroller. refer to the pld section for a detailed description. 9.4.4.6 enable out the enable out register can be read by the microcontroller. it contains the output enable values for a given port. a ??indicates the driver is in output mode. a ??indicates the driver is in tri-state and the pin is in input mode. register name port mcu access data in a,b,c,d read ?input on pin data out a,b,c,d write/read output micro ? cell a,b,c read ?outputs of micro ? cells write ?loading micro ? cells flip-flop mask micro ? cell a,b,c write/read ?prevents loading into a given micro ? cell input micro ? cell a,b,c read ?outputs of the input micro ? cells enable out a,b,c read ?the output enable control of the port driver table 28. port data registers
psd813f family preliminary 64 the psd813f functional blocks (cont.) 9.4.5 ports a and b ? functionality and structure ports a and b have similar functionality and structure, as shown in figure 27. the two ports can be configured to perform one or more of the following functions: o mcu i/o mode o cpld output micro ? cells mcellab[7:0] can be connected to port a or port b. mcellbc[7:0] can be connected to port b or port c. o cpld input via the input micro ? cells. o latched address output ? provide latched address output per table 30. o address in ? additional high address inputs using the input micro ? cells. o open drain/slew rate pins pa[3:0] and pb[3:0] can be configured to fast slew rate, pins pa[7:4] and pb[7:4] can be configured to open drain mode. o data port port a to d[7:0] for 8 bit non-multiplexed bus o multiplexed address/data port for certain types of microcontroller interfaces. o peripheral mode ? port a only
preliminary psd813f family 65 the psd813f functional blocks (cont.) internal data bus data out reg. dq d g q dq dq wr wr wr address micro ? cell outputs enable product term ( .oe ) ale read mux p d b cpld - input control reg. dir reg. input micro ? cell enable out data in output select output mux port a or b pin data out address a [ 7:0 ] or a [ 15:8 ] figure 27. ports a and b structure
psd813f family preliminary 66 the psd813f functional blocks (cont.) 9.4.6 port c ? functionality and structure port c can be configured to perform one or more of the following functions (see figure 29): o mcu i/o mode o cpld output ? mcellbc[7:0] outputs can be connected to port b or port c. o cpld input ? via the input micro ? cells o address in ? additional high address inputs using the input micro ? cells. o in-system programming ? jtag port can be enabled for programming/erase of the psd813f device. (see section 9.6 for more information on jtag programming.) o open drain ? port c pins can be configured in open drain mode o battery backup features pc2 can be configured as a battery input (vstby) pin. pc4 can be configured as a battery on indicator output pin, indicating when vcc is less than vbat. port c does not support address out mode, and therefore no control register is required. pin pc7 may be configured as the dbe input in certain microcontroller interfaces. 9.4.7 port d ? functionality and structure port d has three i/o pins. see figure 30. this port does not support address out mode, and therefore no control register is required. port d can be configured to perform one or more of the following functions: o mcu i/o mode o cpld output ? (external chip select) o cpld input ? direct input to cpld, no input micro ? cells o slew rate ? pins can be set up for fast slew rate port d pins can be configured in psdsoft as input pins for other dedicated functions: o pd0 ? ale, as address strobe input o pd1 ? clkin, as clock input to the micro ? cells flip flops and apd counter o pd2 ? csi, as active low chip select input. a high input will disable the flash/eeprom/sram and csiop. 9.4.7.1 external chip select the cpld also provides three chip select outputs on port d pins that can be used to select external devices. each chip select (ecs0-2) consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register. (see figure 30.)
preliminary psd813f family 67 the psd813f functional blocks (cont.) internal data bus data out reg. dq dq wr wr mcellbc [ 7:0 ] enable product term ( .oe ) read mux p d b cpld - input dir reg. input micro ? cell enable out special function * special function * configuration bit data in output select output mux port c pin data out figure 28. port c structure * isp or battery back-up.
psd813f family preliminary 68 the psd813f functional blocks (cont.) internal data bus data out reg. dq dq wr wr ecs [ 2: 0 ] read mux p d b cpld - input dir reg. data in enable product term (.oe) output select output mux port d pin data out figure 29. port d structure
preliminary psd813f family 69 the psd813f functional blocks (cont.) pld input bus polarity bit pd2 pin pt2 ecs2 direction register polarity bit pd1 pin pt1 ecs1 enable (.oe) enable (.oe) direction register polarity bit pd0 pin pt0 ecs0 enable (.oe) direction register cpld and array figure 30. port d external chip selects
psd813f family preliminary 70 9.5 power management all three device families, the psd813f, zpsd813f, and zpsd813fv offer configurable power saving options. these options may be used individually or in combinations, as follows: o all memory types in a psd (flash, eeprom, and sram) are built with zero-power technology. in addition to using special silicon design methodology, zero-power technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory ?akes up? changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changingit happens automatically. when using zpsd family devices, the pld sections can also achieve standby mode when its inputs are not changing. o like the zero-power feature, the automatic power down (apd) logic allows the psd to reduce to standby current automatically. the apd will block mcu address/data signals from reaching the memories and plds. this feature is available on all three psd813f families. the apd unit is described in more detail in section 9.5.1. built in logic will monitor the address strobe of the mcu for activity. if there is no activity for a certain time period (mcu is asleep), the apd logic initiates power down mode (if enabled). once in power down mode, all address/data signals are blocked from reaching psd memories and plds, and the memories are deselected internally. this allows the memories and plds to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keeps the pld out of standby mode, but not the memories. o the psd chip select input (csi) on all families can be used to disable the internal memories, placing them in standby mode even if inputs are changing. this feature does not block any internal signals or disable the plds. this is a good alternative to using the apd logic, especially if your mcu has a chip select output. there is a slight penalty in memory access time when the csi signal makes its initial transition from deselected to selected. o the pmmr registers can be written by the mcu at run-time to manage power. all three families support ?locking bits?in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figures 34 and 34a). significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations. unique to the zpsd813f and zpsd813fv families is the turbo bit in the pmmr0 register. this bit can be set to disable the turbo mode feature (default is turbo mode on). while turbo mode is disabled, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is enabled. when the turbo mode is enabled, there is a significant dc current component and the ac component is higher. 9.5.1 automatic power down (apd) unit and power down mode the apd unit, shown in figure 31, puts the psd into power down mode by monitoring the activity of the address strobe (ale/as). if the apd unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. if the address strobe remains inactive for fifteen clock periods of the clkin signal, the power down (pdn) signal becomes active, and the psd will enter into power down mode, discussed next. the psd813f functional blocks (cont.)
preliminary psd813f family 71 the psd813f functional blocks (cont.) access 5v v cc , pld memory recovery time typical propagation access to normal standby mode delay time access current power down normal tpd no access tlvdv 50 ? (note 1) (note 2) table 30. psd813f timing and standby current during power down mode notes: 1. power down does not affect the operation of the pld. the pld operation in this mode is based only on the turbo bit. 2. typical current consumption assuming no pld inputs are changing state and the pld turbo bit is off. port function pin level mcu i/o no change pld out no change address out undefined data port three-state peripheral i/o three-state table 29. power down modes effect on ports 9.5.1 automatic power down (apd) unit and power down mode (cont.) power down mode by default, if you enable the psd apd unit, power down mode is automatically enabled. the device will enter power down mode if the address strobe (ale/as) remains inactive for fifteen clkin (pin pd1) clock periods. the following should be kept in mind when the psd is in power down mode: if the address strobe starts pulsing again, the psd will return to normal operation. the psd will also return to normal operation if either the csi input returns low or the reset input returns high. the mcu address/data bus is blocked from all memories and plds. various signals can be blocked (prior to power down mode) from entering the plds by setting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clock (clkin). note that blocking clkin from the plds will not block clkin from the apd unit. all psd memories enter standby mode and are drawing standby current. however, the plds and i/o ports do not go into standby mode because you don? want to have to wait for the logic and i/o to ?ake-up?before their outputs can change. see table 29 for power down mode effects on psd ports. typical standby current is 50 ? for 5 v devices, and 25 ? for 3 v devices. these standby current values assume that there are no transitions on any pld input. hc11 (or compatible) users note the hc11 turns off its e clock when it sleeps. therefore, if you are using an hc11 (or compatible) in your design, and you wish to use the power down, you must not connect the e clock to the clkin input (pd1). you should instead connect an independent clock signal to the clkin input. the clock frequency must be less than 15 times the frequency of as. the reason for this is that if the frequency is greater than 15 times the frequency of as, the psd813f will keep going into power down mode.
psd813f family preliminary 72 apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down ( pdn ) disable bus interface eeprom select flash select sram select pd clr pd disable flash/eeprom/sram pld select figure 31. apd logic block the psd813f functional blocks (cont.) enable apd set pmmr0 bit 1 = 1 psd in power down mode ale/as idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bits 2 through 6. figure 32. enable power down flow chart
preliminary psd813f family 73 bit 1 0 = automatic power down (apd) is disabled. 1 = automatic power down (apd) is enabled. bit 3 0 = pld turbo is on. available in zpsd813f only. 1 = pld turbo is off, saving power. bit 4 0 = clkin input to the pld and array is connected. every clkin change will power up the pld when turbo bit is off. 1 = clkin input to pld and array is disconnected, saving power. bit 5 0 = clkin input to the pld micro ? cells is connected. 1 = clkin input to pld micro ? cells is disconnected, saving power. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ** pld pld pld x apd x mcell clk array clk turbo *** enable 1 = off 1 = off 1 = off 1 = on table 31. power management mode registers (pmmr0, pmmr2)** pmmr0 ** * bits 0, 2, 6, and 7 are not used, and should be set to 0. * ** the pmmr0, and pmmr2 register bits are cleared to zero following power up. *** subsequent reset pulses will not clear the registers. *** zpsd813f and zpsd813fv only. the psd813f functional blocks (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * pld pld pld pld pld ** array array array array array dbe ale cntl2 cntl1 cntl0 1 = off 1 = off 1 = off 1 = off 1 = off pmmr2 bit 2 0 = cntl0 input to the pld and array is connected. 1 = cntl0 input to pld and array is disconnected, saving power. bit 3 0 = cntl1 input to the pld and array is connected. 1 = cntl1 input to pld and array is disconnected, saving power. bit 4 0 = cntl2 input to the pld and array is connected. 1 = cntl2 input to pld and array is disconnected, saving power. bit 5 0 = ale input to the pld and array is connected. 1 = ale input to pld and array is disconnected, saving power. bit 6 0 = dbe input to the pld and array is connected. 1 = dbe input to pld and array is disconnected, saving power. * unused bits should be set to 0.
psd813f family preliminary 74 apd ale enable bit pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (generates pdn after 15 clocks) 1 0 0 counting (generates pdn after 15 clocks) table 32. apd counter operation the psd813f functional blocks (cont.) 9.5.2 other power saving options the psd813f offers other reduced power saving options that are independent of the power down mode. except for the sram standby and csi input features, they are enabled by setting bits in the pmmr0 and pmmr2 registers. 9.5.2.1 zero power pld (zpsd813f) the power and speed of the plds are controlled by the turbo bit (bit 3) in the pmmr0. by setting the bit to ?? the turbo mode is disabled and the plds consume zero power current when the inputs are not switching for an extended time of 70 ns. the propagation delay time will be increased by 10 ns after the turbo bit is set to ??(turned off) when the inputs change at a composite frequency of less than 15 mhz. when the turbo bit is set to a ??(turned on), the plds run at full power and speed. the turbo bit affects the plds d.c. power, ac power, and propagation delay. note: blocking mcu control signals with pmmr2 bits can further reduce pld ac power consumption. 9.5.2.2 sram standby mode (battery backup) the psd813f supports a battery backup operation that retains the contents of the sram in the event of a power loss. the sram has a vstby pin (pc2) that can be connected to an external battery. when v cc becomes lower than vstby then the psd will automatically connect to vstby as a power source to the sram. the sram standby current (istby) is typically 0.5 ?. the sram data retention voltage is 2 v minimum. the battery-on indicator (vbaton) can be routed to pc4. this signal indicates when the v cc has dropped below the vstby voltage. 9.5.2.3 the csi input pin pd2 of port d can be configured in psdsoft as the csi input. when low, the signal selects and enables the internal flash, eeprom, sram, and i/o for read or write operations involving the psd813f. a high on the csi pin will disable the flash memory, eeprom, and sram, and reduce the psd power consumption. however, the pld and i/o pins remain operational when csi is high. note: there may be a timing penalty when using the csi pin depending on the speed grade of the psd that you are using. see the timing parameter t slqv in the ac/dc specs. 9.5.2.4 input clock the psd813f provides the option to turn off the clkin input to the pld to save ac power consumption. the clkin is an input to the pld and array and the output micro ? cells. during power down mode, or, if the clkin input is not being used as part of the pld logic equation, the clock should be disabled to save ac power. the clkin will be disconnected from the pld and array or the micro ? cells by setting bits 4 or 5 to a ??in pmmr0. 9.5.2.5 input control signals the psd813f provides the option to turn off the input control signals (cntl0-2, ale, and dbe) to the pld to save ac power consumption. these control signals are inputs to the pld and array. during power down mode, or, if any of them are not being used as part of the pld logic equation, these control signals should be disabled to save ac power. they will be disconnected from the pld and array by setting bits 2, 3, 4, 5, and 6 to a ??in the pmmr2.
preliminary psd813f family the psd813f functional blocks (cont.) 9.5.3 reset and power on requirement power on reset upon power up the psd813f requires a reset pulse of tnlnh-po (minimum 1ms) after v cc is steady. during this time period the device loads internal configurations, clears some of the registers and sets the flash or eeprom into operating mode. after the rising edge of reset, the psd813f remains in the reset state for an additional topr (minimum 120 ns) nanoseconds before the first memory access is allowed. the psd813f flash or eeprom memory is reset to the read array mode upon power up. the fsi and csbooti select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. the psd automatically prevents write strobes from reaching the eeprom memory array for about 5 ms (teehwl). any flash memory write cycle initiation is prevented automatically when v cc is below vlko. warm reset once the device is up and running, the device can be reset with a much shorter pulse of tnlnh (minimum 150 ns). the same topr time is needed before the device is operational after warm reset. figure 33 shows the timing of the power on and warm reset. 75 operating level power on reset v cc reset t nlnh C po t opr t nlnh t opr warm reset figure 33. power on and warm reset timing i/o pin, register and pld status at reset table 33 shows the i/o pin, register and pld status during power on reset, warm reset and power down mode. pld outputs are always valid during warm reset, and they are valid in power on reset once the internal psd configuration bits are loaded. this loading of psd is completed typically long before the v cc ramps up to operating level. once the pld is active, the state of the outputs are determined by the psdabel equations.
psd813f family preliminary 76 port c pin jtag signals description pc0 tms mode select pc1 tck clock pc3 tstat status pc4 terr error flag pc5 tdi serial data in pc6 tdo serial data out table 34. jtag port signals the psd813f functional blocks (cont.) 9.6 programming in-circuit using the jtag interface the jtag interface on the psd813f can be enabled on port c (see table 34). all memory (flash and eeprom), pld logic, and psd configuration bits may be programmed through the jtag interface. a blank part can be mounted on a printed circuit board and programmed using jtag. the standard jtag signals (ieee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr, are optional jtag extensions used to speed up program and erase operations. by default, on a blank psd (as shipped from factory or after erasure), four pins on port c are enabled for the basic jtag signals tms, tck, tdi, and tdo. see wsi application note 54 for more details on jtag in-system-programming. * sr_cod and periph mode bits in the vm register are always cleared to zero on power on or warm reset. port configuration power on reset warm reset power down mode mcu i/o input mode input mode unchanged pld output valid after internal valid depend on inputs to psd configuration pld (address are bits are loaded blocked in pd mode) address out tri-stated tri-stated not defined data port tri-stated tri-stated tri-stated peripheral i/o tri-stated tri-stated tri-stated table 33. status during power on reset, warm reset and power down mode register power on reset warm reset power down mode pmmr0, 2 cleared to 0 unchanged unchanged micro ? cells flip cleared to 0 by depend on .re and depend on .re and flop status internal power on .pr equations .pr equations reset vm register* initialized based on initialized based on unchanged the selection in the selection in psdsoft psdsoft configuration menu. configuration menu all other registers cleared to 0 cleared to 0 unchanged
preliminary psd813f family 77 9.6.1 standard jtag signals the standard jtag signals (tms, tck, tdi, and tdo) can be enabled by any of three different conditions that are logically ored. when enabled, tdi, tdo, tck, and tms are inputs, waiting for a serial command from an external jtag controller device (such as flashlink or automated test equipment). when the enabling command is received from the external jtag controller, tdo becomes an output and the jtag channel is fully functional inside the psd. the same command that enables the jtag channel may optionally enable the two additional jtag pins, tstat and terr. the following symbolic logic equation specifies the conditions enabling the four basic jtag pins (tms, tck, tdi, and tdo) on their respective port c pins. for purposes of discussion, the logic label jtag_on will be used. when jtag_on is true, the four pins are enabled for jtag. when jtag_on is false, the four pins can be used for general psd i/o. jtag_on = psdsoft_enabled + /* an nvm configuration bit inside the psd is set by the designer in the psdsoft configuration utility. this dedicates the pins for jtag at all times (compliant with ieee 1149.1) */ microcontroller_enabled + /* the microcontroller can set a bit at run-time by writing to the psd register, jtag enable. this register is located at address csiop + offset c7h. setting the jtag_enable bit in this register will enable the pins for jtag use. this bit is cleared by a psd reset or the microcontroller. see table 35 for bit definition. */ psd_product_term_enabled; /* a dedicated product term (pt) inside the psd can be used to enable the jtag pins. this pt has the reserved name jtagsel. once defined as a node in psdabel, the designer can write an equation for jtagsel. this method is used when the port c jtag pins are multiplexed with other i/o signals. it is recommended to logically tie the node jtagsel to the jen\ signal on the flashlink cable when multiplexing jtag signals. see application note 54 for details. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ******* jtag_enable table 35. jtag enable register jtag enable * bits 1-7 are not used and should set to 0. bit definitions: jtag_enable 1 = jtag port is enabled. 0 = jtag port is disabled. the psd813f functional blocks (cont.)
psd813f family preliminary 78 9.6.1 standard jtag signals (cont.) the psd813f supports jtag in-system-configuration (isc) commands, but not boundary scan. a definition of these jtag-isc commands and sequences are defined in a supplemental document available from wsi. wsis psdsoft software tool and flashlink jtag programming cable implement these jtag-isc commands. this document is needed only as a reference for designers who use a flashlink to program their psd813f. 9.6.2 jtag extensions tstat and terr are two jtag extension signals enabled by an ?sc_enable? command received over the four standard jtag pins (tms, tck, tdi, and tdo). they are used to speed programming and erase functions by indicating status on psd pins instead of having to scan the status out serially using the standard jtag channel. see application note 54. terr will indicate if an error has occurred when erasing a sector or programming a byte in flash memory. this signal will go low (active) when an error condition occurs, and stay low until an ?sc_clear?command is executed or a chip reset pulse is received after an ?sc-disable?command. terr does not apply to eeprom. tstat behaves the same as the rdy/bsy signal described in section 9.1.1.2. tstat will be high when the psd813f device is in read array mode (flash memory and eeprom contents can be read). tstat will be low when flash memory programming or erase cycles are in progress, and also when data is being written to eeprom. tstat and terr can be configured as open-drain type signals during an ?sc_enable command. this facilitates a wired-or connection of tstat signals from several psd813f devices and a wired-or connection of terr signals from those same devices. this is useful when several psd813f devices are ?hained?together in a jtag environment. 9.6.3 security and flash memories and eeprom protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program/erase/verify commands are blocked. full chip erase returns the part to a non-secured blank state. the security bit can be set in psdsoft configuration. all flash memory and eeprom sectors can individually be sector protected against erasures. the sector protect bits can be set in psdsoft configuration. the psd813f functional blocks (cont.)
preliminary psd813f family 79 symbol parameter condition min max unit t stg storage temperature pldcc ?65 + 125 ? commercial 0 + 70 ? operating temperature industrial ?40 + 85 ? voltage on any pin with respect to gnd ?0.6 + 7 v v pp device programmer supply voltage with respect to gnd ?0.6 + 14 v v cc supply voltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. symbol parameter condition min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v cc supply voltage v-versions 2.7 3.6 v all speeds recommended operating conditions range temperature v cc tolerance commercial 0 c to +70? + 5 v 10% industrial 40 c to +85? + 5 v 10% commercial 0 c to +70? 2.7 v to 3.6 v industrial 40 c to +85? 2.7 v to 3.6 v operating range
psd813f family preliminary 80 ac/dc parameters the following tables describe the ad/dc parameters of the psd813f family: o dc electrical specification o ac timing specification pld timing combinatorial timing synchronous clock mode asynchronous clock mode input micro ? cell timing microcontroller timing read timing write timing peripheral mode timing power down and reset timing following are issues concerning the parameters presented: o in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd813f is in each mode. also, the supply power is considerably different if the turbo bit is "off" (zpsd813f and zpsd813fv). o the ac power component gives the pld, eprom, and sram ma/mhz specification. figures 34 and 34a show the pld ma/mhz as a function of the number of product terms (pt) used. o in the pld timing parameters, add the required delay when turbo bit is "off". figure 34. pld i cc /frequencyconsumption (v cc = 5 v 10%) 0 10 20 30 40 60 70 80 90 100 110 v cc = 5v 50 01015 5 20 25 highest composite frequency at pld inputs (mhz) i cc ?(ma) turbo on (100%) turbo on (25%) turbo off turbo off pt 100% pt 25%
preliminary psd813f family 81 figure 34a. pld i cc /frequency consumption (psd813fv versions, v cc = 3 v 10%) 0 10 20 30 40 50 60 v cc = 3v 01015 5 20 25 i cc ?(ma) turbo on (100%) turbo on (25%) turbo off turbo off highest composite frequency at pld inputs (mhz) pt 100% pt 25% conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = on calculation (typical numbers used) i cc total = ipwrdown x %pwrdown + %normal x ( i cc (ac) + i cc (dc) ) = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x 2 ma/mhz x freq pld + #pt x 400 a/pt = 50 a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz +2 ma/mhz x 8 mhz + 45 x 0.4 ma/pt) = 45 a + 0.1 x (8 + 0.9 + 16 + 18 ma) = 45 a + 0.1 x 42.9 = 45 a + 4.29 ma = 4.34 ma this is the operating power with no eeprom writes or flash erases. calculation is based on i out = 0 ma. example of psd813f typical power calculation at v cc = 5.0 v ac/dc parameters (cont.)
psd813f family preliminary 82 conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = off calculation (typical numbers used) i cc total = ipwrdown x %pwrdown + %normal x ( i cc (ac) + i cc (dc) ) = ipwrdown x %pwrdown + % normal x ( %flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x (from graph using freq pld) ) = 50 a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz + 24 ma) = 45 a + 0.1 x (8 + 0.9 + 24) = 45 a + 0.1 x 32.9 = 45 a + 3.29 ma = 3.34 ma this is the operating power with no eeprom writes or flash erases. calculation is based on i out = 0 ma. example of zpsd813f typical power calculation at v cc = 5.0 v ac/dc parameters (cont.)
preliminary psd813f family 83 symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high level input voltage 4.5 v < v cc < 5.5 v 2 v cc +.5 v v il low level input voltage 4.5 v < v cc < 5.5 v .5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v lko v cc min for flash erase and program 2.5 4.2 v v ol output low voltage i ol = 20 a, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.25 0.45 v v oh output high voltage except v stby on i oh = 20 a, v cc = 4.5 v 4.4 4.49 v i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v oh 1 output high voltage v stby on i oh 1 = 1 a v sby ?0.8 v v sby sram standby voltage 2.0 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 a v df sram data retention voltage only on v stby 2v i li input leakage current v ss < v in < v cc ? .1 1 a i lo output leakage current 0.45 < v in > v cc ?0 5 10 a psd813f/zpsd813f dc characteristics (5 v 10% versions) notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc .
psd813f family preliminary 84 notes: 1. csi deselected or internal power down mode is active. 2. pld is in non-turbo mode and none of the inputs are switching. 3. refer to figure 34 for pld current calculation. 4. i out = 0 ma symbol parameter conditions min typ max unit zpld_turbo = off, 0ma f = 0 mhz (note 4) zpld only zpld_turbo = on, f = 0 mhz 400 700 a/pt i cc (dc) operating during flash or eeprom (note 4) supply current flash or eeprom write/erase only 30 60 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma i cc (ac) zpld ac adder figure 34 (note 4) flash or eeprom ac adder 2.5 3.5 ma/mhz sram ac adder 1.5 3.0 ma/mhz i sb standby supply current for csi > v cc ?.3 v 50 200 a power down mode (notes 1 and 2) zpsd813f dc characteristics (i cc ) symbol parameter conditions min typ max unit pld only f = 0 mhz 400 700 a/pt i cc (dc) operating during flash or eeprom 30 60 ma (note 4) supply current flash or eeprom write/erase only read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma pld ac adder 2 3 ma/mhz i cc (ac) flash or eeprom ac adder 2.5 3.5 ma/mhz (note 4) sram ac adder 1.5 3.0 ma/mhz i sb standby supply current for csi > v cc ?.3 v 200 a + pld current ? power down mode (note 1) (note 3) psd813f dc characteristics (i cc )
preliminary psd813f family 85 -90 -12 -15 fast pt turbo slew symbol parameter conditions min max min max min max aloc off * (note 1) unit t pd cpld input pin/feedback to 25 30 32 add 2 add 10 sub 2 ns cpld combinatorial output t ea cpld input to cpld output enable 26 30 32 add 10 sub 2 ns t er cpld input to cpld output disable 26 30 32 add 10 sub 2 ns t arp cpld register clear or preset delay 26 30 33 add 10 sub 2 ns t arpw cpld register clear or 20 24 29 add 10 ns preset pulse width t ard cpld array delay any 16 18 22 add 2 ns micro ? cell cpld combinatorial timing (5 v 10%) note: 1. fast slew rate output available on pa[3:0], pb[3:0], and pd[2:0]. * zpsd versions only. psd813f ac/dc parameters C cpld timing parameters (5 v 10% versions)
psd813f family preliminary 86 -90 -12 -15 fast pt turbo slew symbol parameter conditions min max min max min max aloc off * (note 1) unit maximum frequency external feedback 1/(t s +t co ) 30.30 26.3 23.8 mhz maximum frequency f max internal feedback 1/(t s +t co ?0) 43.48 35.7 31.25 mhz (f cnt ) maximum frequency pipelined data 1/(t ch +t cl ) 50.00 41.67 33.3 mhz t s input setup time 15 18 20 add 2 add 10 ns t h input hold time 0 0 0 ns t ch clock high time clock input 10 12 15 ns t cl clock low time clock input 10 12 15 ns t co clock to output delay clock input 18 20 22 sub 2 ns t ard cpld array delay any micro ? cell 16 18 22 add 2 ns t min minimum clock period t ch +t cl (note 2) 20 24 30 ns cpld micro ? cell synchronous clock mode timing (5 v 10% versions) notes: 1. fast slew rate output available on pa[3:0], pb[3:0], and pd[2:0]. 2. clkin t clcl = t ch + t cl . * zpsd versions only. psd813f ac/dc parameters C cpld timing parameters (5 v 10% versions)
preliminary psd813f family 87 -90 -12 -15 pt turbo slew symbol parameter conditions min max min max min max aloc off * rate unit maximum frequency external feedback 1/(t sa +t co a ) 26.32 23.25 20.4 mhz maximum frequency f maxa internal feedback 1/(t sa +t co a ?0) 35.71 30.30 25.64 mhz (f cnta ) maximum frequency pipelined data 1/(t cha +t cla ) 41.67 35.71 33.3 mhz t sa input setup time 8 10 12 add 2 add 10 ns t ha input hold time 12 14 14 ns t cha clock input high time 12 14 15 add 10 ns t cla clock input low time 12 14 15 add 10 ns t coa clock to output delay 30 33 37 add 10 sub 2 ns t arda cpld array delay any micro ? cell 16 18 22 add 2 ns t mina minimum clock period 1/ f cnta 28 33 39 ns cpld micro ? cell asynchronous clock mode timing (5 v 10% versions) * zpsd versions only. psd813f ac/dc parameters C cpld timing parameters (5 v 10% versions)
psd813f family preliminary 88 -90 -12 15 pt turbo symbol parameter conditions min max min max min max aloc off * unit t is input setup time (note 1) 0 0 0 ns t ih input hold time (note 1) 20 22 26 add 10 ns t inh nib input high time (note 1) 12 15 18 ns t in l nib input low time (note 1) 12 15 18 ns t ino nib input to combinatorial delay (note 1) 46 50 59 add 2 add 10 ns input micro ? cell timing (5 v 10% versions) note: 1. inputs from port a, b, and c relative to register/latch clock from the pld. ale/as latch timings refer to t avlx and t lxax . * zpsd versions only. psd813f ac/dc parameters C cpld timing parameters (5 v 10% versions)
preliminary psd813f family 89 ac symbols for pld timing. example: t avlx ? time from address valid to ale invalid. signal letters a address input c ceout output d input data e e input g internal wdog_on signal i interrupt input l ale input n reset input or output p port signal output q output data r wr, uds, lds, ds, iord, psen inputs s chip select input t r/w input w internal pdn signal b vstby output m output micro ? cell signal behavior t time l logic level low or ale h logic level high v valid x no longer a valid logic level z float pw pulse width microcontroller interface C ac/dc parameters (5v 10% versions)
psd813f family preliminary 90 notes: 1. rd timing has the same timing as ds, lds, uds, and psen signals. 2. rd and psen have the same timing. 3. any input used to select an internal psd813f function. 4. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 5. rd timing has the same timing as ds, lds, and uds signals. -90 -12 -15 turbo symbol parameter conditions min max min max min max off unit t lvlx ale or as pulse width 20 22 28 ns t avlx address setup time (note 3) 6 8 10 ns t lxax address hold time (note 3) 8 9 11 ns t avqv address valid to data valid (note 3) 90 120 150 add 10 ns t slqv cs valid to data valid 100 135 150 ns rd to data valid 8-bit bus (note 5) 32 35 40 ns t rlqv rd or psen to data valid 8-bit bus, 8031, 80251 (note 2) 38 42 45 ns t rhqx rd data hold time (note 1) 0 0 0 ns t rlrh rd pulse width (note 1) 32 35 38 ns t rhqz rd to data high-z (note 1) 25 29 33 ns t ehel e pulse width 32 36 38 ns t theh r/w setup time to enable 10 13 18 ns t eltl r/w hold time after enable 0 0 0 ns t avpv address input valid to (note 4) 32 40 48 ns address output delay read timing (5 v 10% versions) microcontroller interface C psd813f ac/dc parameters (5v 10% versions)
preliminary psd813f family 91 -90 -12 -15 symbol parameter conditions min max min max min max unit t lvlx ale or as pulse width 20 22 28 t avlx address setup time (note 1) 6 8 10 ns t lxax address hold time (note 1) 8 9 11 ns t avwl address valid to leading edge of wr (notes 1 and 3) 20 25 30 ns t slwl cs valid to leading edge of wr (note 3) 25 30 35 ns t dvwh wr data setup time (note 3) 35 40 45 ns t whdx wr data hold time (note 3) 5 5 5 ns t wlwh wr pulse width (note 3) 35 40 45 ns t whax trailing edge of wr to address invalid (note 3) 0 0 0 ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3) 30 35 38 ns t wlmv wr valid to port output valid using micro ? cell register preset/clear (notes 3 and 4) 55 60 65 ns also including t whqv1 byte programming operation pre-programming 14 14 14 s time t whqv2 sector erase operation note 100% tested 2.2 2.2 2.2 sec t q7vqv q7 valid to output valid (data polling) 60 65 70 ns t vcs v cc setup time v cc high to first flash wr low 45 48 50 s data valid to port output valid t dvmv using micro ? cell register (notes 3 and 5) 55 60 65 ns preset/clear t avpv address input valid to address (note 2) 32 40 48 ns output delay write, erase and program timing (5 v 10% versions) notes: 1. any input used to select an internal psd813f function. 2. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 3. wr timing has the same timing as e, lds, uds, wrl, and wrh signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. microcontroller interface C psd813f ac/dc parameters (5v 10% versions)
psd813f family preliminary 92 -90 -12 -15 turbo symbol parameter conditions min max min max min max off unit t avqv (pa) address valid to data valid (note 3) 55 59 62 add 10 ns t slqv (pa) csi valid to data valid 55 59 62 add 10 ns rd to data valid (notes 1 and 4) 32 35 40 ns t rlqv (pa) rd to data valid 8031 mode 38 42 45 ns t dvqv (pa) data in to data out valid 40 43 45 ns t qxrh (pa) rd data hold time 0 0 0 ns t rlrh (pa) rd pulse width (note 1) 32 35 38 ns t rhqz (pa) rd to data high-z (note 1) 25 30 33 ns port a peripheral data mode read timing (5 v 10%) -90 -12 -15 symbol parameter conditions min max min max min max unit t wlqv (pa) wr to data propagation delay (note 2) 35 38 40 ns t dvqv (pa) data to port a data propagation delay (note 5) 40 43 45 ns t whqz (pa) wr invalid to port a tri-state (note 2) 25 30 33 ns port a peripheral data mode write timing (5 v 10%) notes: 1. rd timing has the same timing as ds, lds, uds, and psen (in 8031 combined mode) signals. 2. wr timing has the same timing as e, lds, uds, wrl, and wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. microcontroller interface C psd813f ac/dc parameters (5v 10% versions)
preliminary psd813f family 93 symbol parameter conditions min typ max unit t nlnh warm reset active low time (note 1) 150 ns t opr reset high to operational device 120 ns t nlnh-po power on reset active low time 1ms (note 2) reset timing (5 v 10%) note: 1. t clcl is the clkin clock period. microcontroller interface C psd813f ac/dc parameters (5v 10% versions) symbol parameter conditions min typ max unit t bvbh vstby detection to vstbyon output high 20 s t bxbl v stby off detection to v stbyon output low 20 s v stbyon timing (5 v 10%) -90 -12 -15 symbol parameter conditions min max min max min max unit t lvdv ale access time from power down 120 135 150 ns maximum delay from t clwh apd enable to internal using clkin input 15 * t clcl (note 1) s pdn valid signal power down timing (5 v 10%) note: 1. reset will not reset flash or eeprom programming/erase cycles. 2. tnlnh-po is 10 ms for devices manufactured before rev. a.
psd813f family preliminary 94 -90 -12 -15 symbol parameter conditions min max min max min max unit t isccf tck clock frequency (except for pld) (note 1) 18 16 14 mhz t iscch tck clock high time (note 1) 26 29 31 ns t isccl tck clock low time (note 1) 26 29 31 ns t isccf-p tck clock frequency (for pld only) (note 2) 2 2 2 mhz t iscch-p tck clock high time (for pld only) (note 2) 240 240 240 ns t isccl-p tck clock low time (for pld only) (note 2) 240 240 240 ns t iscpsu isc port set up time 8 10 10 ns t iscph isc port hold up time 5 5 5 ns t iscpco isc port clock to output 23 24 25 ns t iscpzv isc port high-impedance to valid output 23 24 25 ns t iscpvz isc port valid output to high-impedance 23 24 25 ns isc timing (5 v 10%) microcontroller interface C psd813f ac/dc parameters (5v 10% versions) symbol parameter min typ max unit flash program 8.5 sec flash bulk erase (preprogrammed) (note 1) 3 30 sec flash bulk erase (not preprogrammed) 10 sec t whqv3 sector erase (preprogrammed) 1 30 sec t whqv2 sector erase (not preprogrammed) 2.2 sec t whqv1 byte program 14 1200 s program/erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s flash program, write and erase times (5 v 10%) note: 1. programmed to all zeros before erase. symbol parameter min typ max unit t eehwl write protect after power up 5 msec t blc eeprom byte load cycle timing (note 1) 0.2 120 sec t wcb eeprom byte write cycle time 4 10 msec t wcp eeprom page write cycle time (note 2) 6 30 msec program/erase cycles (per sector) 10,000 cycles eeprom write times (5 v 10%) notes: 1. if the maximum time has elapsed between successive writes to an eeprom page, the transfer of this data to eeprom cells will begin. also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type. 2. these specifications are for writing a page to eeprom cells. notes: 1. for ?on-pld?programming, erase or in isc by-pass mode. 2. for program or erase pld only.
preliminary psd813f family 95 symbol parameter conditions min typ max unit v cc supply voltage all speeds 2.7 3.6 v v ih high level input voltage 2.7 v < v cc < 3.6 v .7 v cc v cc +.5 v v il low level input voltage 2.7 v < v cc < 3.6 v .5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v lko v cc min for flash erase and program 1.9 2.2 v v ol output low voltage i ol = 20 a, v cc = 2.7 v 0.01 0.1 v i ol = 4 ma, v cc = 2.7 v 0.15 0.45 v v oh output high voltage except v stby on i oh = 20 a, v cc = 2.7 v 2.6 2.69 v i oh = 1 ma, v cc = 2.7 v 2.3 2.4 v v oh 1 output high voltage v stby on i oh 1 = 1 a v sby ?0.8 v v sby sram standby voltage 2.0 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb standby supply current csi >v cc ?.3 v (note 2) 25 100 a for power down mode i li input leakage current v ss < v in < v cc ? .1 1 a i lo output leakage current 0.45 < v in > v cc ?0 5 10 a zpld_turbo = off, f = 0 mhz (note 3) 0ma zpld only zpld_turbo = on, i cc (dc) operating f = 0 mhz 200 400 a/pt (note 3) supply current during flash or flash or eeprom eeprom write/erase only 10 25 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma zpld ac adder figure 34a i cc (ac) flash or (note 3) eeprom 2 2.5 ma/mhz ac adder sram ac adder 0.8 1.5 ma/mhz zpsd813fv dc characteristics (2.7 v to 3.6 v versions) notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal pd is active. 3. i out = 0 ma
psd813f family preliminary 96 zpsd813fv ac/dc parameters C cpld timing parameters (2.7 v to 3.6 v versions) -15 -20 slew pt turbo rate symbol parameter conditions min max min max aloc off * (note 1) unit cpld input pin/feedback to t pd cpld combinatorial output 48 55 add 4 add 20 sub 6 ns t ea cpld input to cpld output enable 43 50 add 20 sub 6 ns t er cpld input to cpld output disable 43 50 add 20 sub 6 ns t arp cpld register clear or preset delay 48 55 add 20 sub 6 ns t arpw cpld register clear or 30 35 add 20 ns preset pulse width t ard cpld array delay any micro ? cell 29 33 add 4 ns cpld combinatorial timing (2.7 v to 3.6 v versions) -15 -20 slew pt turbo rate symbol parameter conditions min max min max aloc off * (note 1) unit maximum frequency external feedback 1/(t s +t co ) 17.8 14.7 mhz maximum frequency f max internal feedback ( f cnt ) 1/(t s +t co ?0) 19.6 17.2 mhz maximum frequency pipelined data 1/(t ch +t cl ) 33.3 31.2 mhz t s input setup time 27 35 add 4 add 20 ns t h input hold time 0 0 ns t ch clock high time clock input 15 16 ns t cl clock low time clock input 15 16 ns t co clock to output delay clock input 35 39 sub 6 ns t ard cpld array delay any micro ? cell 29 33 add 4 ns t min minimum clock period t ch +t cl (note 2) 29 32 ns cpld micro ? cell synchronous clock mode timing (2.7 v to 3.6 v versions) notes: 1. fast slew rate output available on pa[3:0], pb[3:0], and pd[2:0]. 2. clkin t clcl = t ch + t cl . * zpsd versions only. note: 1. fast slew rate output available on pa[3:0], pb[3:0], and pd[2:0]. * zpsd versions only.
preliminary psd813f family 97 -15 -20 pt turbo slew symbol parameter conditions min max min max aloc off * rate unit maximum frequency external feedback 1/(t sa +t co a ) 16.9 14.7 mhz maximum frequency f maxa internal feedback ( f cnta ) 1/(t sa +t co a ?0) 20.4 17.2 mhz maximum frequency pipelined data 1/(t cha +t cla ) 27 24.4 mhz t sa input setup time 12 13 add 4 add 20 ns t ha input hold time 15 17 ns t cha clock high time 22 25 add 20 ns t cla clock low time 15 16 add 20 ns t coa clock to output delay 47 55 add 20 sub 6 ns t ard cpld array delay any micro ? cell 29 33 add 4 ns t mina minimum clock period 1/ f cnta 43 58 ns cpld micro ? cell asynchronous clock mode timing (2.7 v to 3.6 v versions) note: 1. inputs from port a, b, and c relative to register/latch clock from the pld. ale latch timings refer to t avlx and t lxax . * zpsd versions only. -15 -20 pt turbo symbol parameter conditions min max min max aloc off * unit t is input setup time (note 1) 0 0 ns t ih input hold time (note 1) 30 35 add 20 ns t inh nib input high time (note 1) 13 15 ns t in l nib input low time (note 1) 13 15 ns t ino nib input to combinatorial delay (note 1) 90 100 add 4 add 20 ns input micro ? cell timing (2.7 v to 3.6 v versions) zpsd813fv ac/dc parameters C cpld timing parameters (2.7 v to 3.6 v versions) * zpsd versions only.
psd813f family preliminary 98 ac symbols for pld timing. example: t avlx ? time from address valid to ale invalid. signal letters a address input c ceout output d input data e e input g internal wdog_on signal i interrupt input l ale input n reset input or output p port signal output q output data r wr, uds, lds, ds, iord, psen inputs s chip select input t r/w input w internal pdn signal b vstby output m output micro ? cell signal behavior t time l logic level low or ale h logic level high v valid x no longer a valid logic level z float pw pulse width microcontroller interface C zpsd813fv ac/dc parameters (3v 10% versions)
preliminary psd813f family 99 -15 -20 turbo symbol parameter conditions min max min max off unit t lvlx ale or as pulse width 28 30 ns t avlx address setup time (note 3) 10 12 ns t lxax address hold time (note 3) 12 14 ns t avqv address valid to data valid (note 3) 150 200 add 20 ns t slqv cs valid to data valid 150 200 ns rd to data valid 8-bit bus (note 5) 35 40 ns t rlqv rd or psen to data valid 8-bit bus, 8031, 80251 (note 2) 50 55 ns t rhqx rd data hold time (note 1) 0 0 ns t rlrh rd pulse width (also ds, lds, uds) 40 45 ns rd or psen pulse width (8031, 80251) 55 60 ns t rhqz rd to data high-z (note 1) 45 45 ns t ehel e pulse width 52 57 ns t theh r/w setup time to enable 18 20 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to (note 4) 48 50 ns address output delay read timing (2.7 v to 3.6 v versions) microcontroller interface C zpsd813fv ac/dc parameters (2.7 v to 3.6 v versions) notes: 1. rd timing has the same timing as ds, lds, uds, and psen signals. 2. rd and psen have the same timing for 8031. 3. any input used to select an internal psd813f function. 4. in multiplexed mode latched address generated from adio delay to address output on any port. 5. rd timing has the same timing as ds, lds, and uds signals.
psd813f family preliminary 100 -15 -20 symbol parameter conditions min max min max unit t lvlx ale or as pulse width 28 30 t avlx address setup time (note 1) 10 12 ns t lxax address hold time (note 1) 12 14 ns t avwl address valid to leading edge of wr (notes 1 and 3) 30 35 ns t slwl cs valid to leading edge of wr (note 3) 34 40 ns t dvwh wr data setup time (note 3) 45 50 ns t whdx wr data hold time (note 3) 8 10 ns t wlwh wr pulse width (note 3) 48 53 ns t whax trailing edge of wr to address invalid (note 3) 0 0 ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3) 45 50 ns t wlmv wr valid to port output valid using micro ? cell register preset/clear (notes 3 and 4) 90 100 ns t whqv1 byte programming operation also including pre-programming time 14 14 s t whqv2 sector erase operation note 100% tested 2.2 2.2 sec t q7vqv q7 valid to output valid (data polling) 70 75 ns t vcs v cc setup time v cc high to first flash wr low 45 50 s t dvmv data valid to port output valid using micro ? cell register preset/clear (notes 3 and 5) 90 100 ns t avpv address input valid to address (note 2) 48 55 ns output delay write, erase and program timing (2.7 v to 3.6 v versions) notes: 1. any input used to select an internal psd813f function. 2. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 3. wr timing has the same timing as e, lds, uds, wrl, and wrh signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. microcontroller interface C zpsd813fv ac/dc parameters (2.7 v to 3.6 v versions)
preliminary psd813f family 101 -15 -20 symbol parameter conditions min max min max unit t wlqv (pa) wr to data propagation delay (note 2) 45 55 ns t dvqv (pa) data to port a data propagation delay (note 5) 50 55 ns t whqz (pa) wr invalid to port a tri-state (note 2) 33 35 ns port a peripheral data mode write timing (2.7 v to 3.6 v versions) microcontroller interface C zpsd813fv ac/dc parameters (2.7 v to 3.6 v versions) notes: 1. rd timing has the same timing as ds, lds, uds, and psen (in 8031 combined mode) signals. 2. wr timing has the same timing as e, lds, uds, wrl, and wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. -15 -20 turbo symbol parameter conditions min max min max off unit t avqv (pa) address valid to data valid (note 3) 87 95 add 20 ns t slqv (pa) csi valid to data valid 70 80 add 20 ns rd to data valid (notes 1 and 4) 40 45 ns t rlqv (pa) rd to data valid 8031 mode 45 50 ns t dvqv (pa) data in to data out valid 50 55 ns t qxrh (pa) rd data hold time 0 0 ns t rlrh (pa) rd pulse width (note 1) 36 46 ns t rhqz (pa) rd to data high-z (note 1) 32 35 ns port a peripheral data mode read timing (2.7 v to 3.6 v versions)
psd813f family preliminary 102 -15 -20 symbol parameter conditions min max min max unit t lvdv ale access time from power down 150 200 ns maximum delay from apd enable t clwh to internal pdn valid signal using clkin input 15 * t clcl (note 1) s power down timing (2.7 v to 3.6 v versions) symbol parameter conditions min typ max unit t nlnh warm reset active low time (note 1) 300 ns t opr reset high to operational device 300 ns t nlnh-po power on reset active low time 1ms (note 2) reset timing (2.7 v to 3.6 v versions) note: 1. t clcl is the clkin clock period. microcontroller interface C zpsd813fv ac/dc parameters (2.7 v to 3.6 v versions) symbol parameter conditions min typ max unit t bvbh v stby detection to v stbyon output high 2.0 s t bxbl v stby off detection to v stbyon output low 2.0 s v stbyon timing (2.7 v to 3.6 v versions) note: 1. reset will not reset flash or eeprom programming/erase cycles. 2. tnlnh-po is 10 ms for devices manufactured before the rev. a.
preliminary psd813f family 103 microcontroller interface C zpsd813fv ac/dc parameters (2.7 v to 3.6 v versions) symbol parameter min typ max unit flash program 8.5 sec flash bulk erase (preprogrammed) (note 1) 3 30 sec flash bulk erase (not preprogrammed) 10 sec t whqv3 sector erase (preprogrammed) 1 30 sec t whqv2 sector erase (not preprogrammed) 2 sec t whqv1 byte program 10 1200 s program/erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s flash program, write and erase times (2.7 v to 3.6 v versions) -15 -20 symbol parameter conditions min max min max unit t isccf tck clock frequency (except for pld) (note 1) 10 9 mhz t iscch tck clock high time (note 1) 45 51 ns t isccl tck clock low time (note 1) 45 51 ns t isccf-p tck clock frequency (for pld only) (note 2) 2 2 mhz t iscch-p tck clock high time (for pld only) (note 2) 240 240 ns t isccl-p tck clock low time (for pld only) (note 2) 240 240 ns t iscpsu isc port set up time 13 15 ns t iscph isc port hold up time 5 5 ns t iscpco isc port clock to output 36 40 ns t iscpzv isc port high-impedance to valid output 36 40 ns t iscpvz isc port valid output to high-impedance 36 40 ns isc timing (2.7 v to 3.6 v versions) notes: 1. programmed to all zeros before erase. symbol parameter min typ max unit t eehwl write protect after power up 5 msec t blc eeprom byte load cycle timing (note 1) 0.2 120 sec t wcb eeprom byte write cycle time 4 10 msec t wcp eeprom page write cycle time (note 2) 6 30 msec program/erase cycles (per sector) 10,000 cycles eeprom write times (2.7 v to 3.6 v versions) notes: 1. if the maximum time has elapsed between successive writes to an eeprom page, the transfer of this data to eeprom cells will begin. also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type. 2. these specifications are for writing a page to eeprom cells. notes: 1. for ?on-pld?programming, erase or in isc by-pass mode. 2. for program or erase pld only.
psd813f family preliminary 104 figure 35. read timing t avlx t lxax * t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) e r/w * t avlx and t lxax are not required for 80c251 in page mode or 80c51xa in burst mode.
preliminary psd813f family 105 figure 36. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale/as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w
psd813f family preliminary 106 figure 38. peripheral i/o write timing figure 37. peripheral i/o read timing t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address data valid ale /as a /d bus rd data on port a csi tdvqv (pa) twlqv (pa) twhqz (pa) address data out a /d bus wr port a data out ale /as
preliminary psd813f family 107 figure 39. combinatorial timing C pld t pd cpld input cpld output figure 40. synchronous clock mode timing C pld t ch t cl t co t h t s clkin input registered output
psd813f family preliminary 108 figure 41. asynchronous clock mode timing (product-term clock) figure 42. input micro ? cell timing (product-term clock) tcha tcla tcoa tha tsa clock input registered output t inh t inl t ino t ih t is pt clock input output
preliminary psd813f family 109 figure 43. input to output disable / enable figure 44. asynchronous reset/ preset ter tea input input to output enable/disable tarp register output tarpw reset/preset input figure 45. isc timing qq q #u q(u# q(u# qq q q q q qq
psd813f family preliminary 110 figure 46. reset timing figure 47. key to switching waveforms operating level power on reset v cc reset t nlnh po t opr t nlnh t opr warm reset waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state
preliminary psd813f family 111 symbol parameter 1 conditions typical 2 max unit c in capacitance (for input pins only) v in = 0 v 4 6 pf c out capacitance (for input/output pins) v out = 0 v 8 12 pf c vpp capacitance (for cntl2/v pp )v pp = 0 v 18 25 pf notes: 1. these parameters are only sampled and are not 100% tested. 2. typical values are for t a = 25 c and nominal supply voltages. t a = 25 ?, f = 1 mhz pin capacitance figure 48. ac testing input/output waveform figure 49. ac testing load circuit programming 3.0v 0v test point 1.5v device under test 2.01 v 195 ? c l = 30 pf (including scope and jig capacitance) upon delivery from wsi, the psd813f device has all bits in the plds and memories in the 1 or high state. the configuration bits are in the 0 or low state. the code, configuration, and plds logic are loaded through the procedure of programming. information for programming the device is available directly from wsi. please contact your local sales representative. (see the last page.)
psd813f family preliminary 112 psd813f pin assignments pin no. pin assignments pin no. pin assignments 1 gnd 27 pa2 2 pb5 28 pa1 3 pb4 29 pa0 4 pb3 30 ad0 5 pb2 31 ad1 6 pb1 32 ad2 7 pb0 33 ad3 8 pd2 34 ad4 9 pd1 35 ad5 10 pd0 36 ad6 11 pc7 37 ad7 12 pc6 38 v cc 13 pc5 39 ad8 14 pc4 40 ad9 15 v cc 41 ad10 16 gnd 42 ad11 17 pc3 43 ad12 18 pc2 (vstby) 44 ad13 19 pc1 45 ad14 20 pc0 46 ad15 21 pa7 47 cntl0 22 pa6 48 reset 23 pa5 49 cntl2 24 pa4 50 cntl1 25 pa3 51 pb7 26 gnd 52 pb6 52-pin plastic leaded chip carrier (pldcc) (package type j)
preliminary psd813f family 113 psd813f pin assignments (cont.) pin no. pin assignments pin no. pin assignments 1 pd2 33 ad3 2 pd1 34 ad4 3 pd0 35 ad5 4 pc7 36 ad6 5 pc6 37 ad7 6 pc5 38 v cc 7 pc4 39 v cc 8v cc 40 ad8 9v cc 41 ad9 10 gnd 42 ad10 11 gnd 43 ad11 12 pc3 44 ad12 13 pc2 45 ad13 14 pc1 46 ad14 15 pc0 47 ad15 16 n/c 48 cntl0 17 n/c 49 n/c 18 n/c 50 reset 19 pa7 51 cntl2 20 pa6 52 cntl1 21 pa5 53 pb7 22 pa4 54 pb6 23 pa3 55 gnd 24 gnd 56 gnd 25 gnd 57 pb5 26 pa2 58 pb4 27 pa1 59 pb3 28 pa0 60 pb2 29 ad0 61 pb1 30 ad1 62 pb0 31 n/c 63 n/c 32 ad2 64 n/c 64-pin plastic thin quad flatpack (tqfp) (package type u)
psd813f family preliminary 114 psd813f package information 1 pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntl0 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 51 50 49 48 47 52 46 45 44 43 42 41 40 39 38 37 36 35 34 8 9 10 11 12 13 14 15 16 17 18 19 20 765432 v cc pd2 pd1 pd0 pc7 pc6 pc5 pc4 gnd pc3 pc2 (vstby) pc1 pc0 ad15 ad14 ad13 ad12 ad11 ad10 v cc ad8 ad9 ad7 ad6 ad5 ad4 21 22 23 24 25 26 27 28 29 30 31 32 33 figure 50. drawing j7 C 52-pin plastic leaded chip carrier (pldcc) (package type j) 48 cntl 0 47 ad15 46 ad14 45 ad13 44 ad12 43 ad11 42 ad10 41 ad9 40 ad8 39 v cc 38 v cc 37 ad7 36 ad6 35 ad5 34 ad4 33 ad3 pd2 pd1 pd0 pc7 pc6 pc5 pc4 v cc v cc gnd gnd pc3 pc2 pc1 pc0 n/c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 n/c n/c pb0 pb1 pb2 pb3 pb4 pb5 gnd gnd pb6 pb7 cntl1 cntl2 reset n/c 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 n/c n/c pa7 pa6 pa5 pa4 pa3 gnd gnd pa2 pa1 pa0 ad0 ad1 n/c ad2 figure 51. drawing u4 C 64-pin plastic thin quad flatpack (tqfp) (package type u)
preliminary psd813f family 115 family: plastic leaded chip carrier millimeters inches symbol min max notes min max notes a 4.19 4.57 0.165 0.180 a1 2.54 2.79 0.100 0.110 a2 3.66 3.86 0.144 0.152 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 c 0.246 0.261 0.0097 0.0103 d 19.94 20.19 0.785 0.795 d1 19.05 19.15 0.750 0.754 d2 17.53 18.54 0.690 0.730 d3 15.24 reference 0.600 reference e 19.94 20.19 0.785 0.795 e1 19.05 19.15 0.750 0.754 e2 17.53 18.54 0.690 0.730 e3 15.24 reference 0.600 reference e1 1.27 reference 0.050 reference n52 52 020197r1 figure 50a. drawing j7 C 52-pin plastic leaded chip carrier (pldcc) (package type j) e1 e 52 51 1 2 3 d1 d view a r .025 .045 d3 b1 b a1 a d2 a2 c e3 e1 view a e2
psd813f family preliminary 116 figure 51a. drawing u4 C 64-pin plastic thin quad flatpack (tqfp) (package type u) d d1 d3 e3 e1 e index mark standoff: 0.05 mm min. lead coplanarity: 0.1mm max. l c a2 b 64 1 2 3 e1 a family: plastic thin quad flatpack (tqfp) millimeters inches symbol min max notes min max notes 0 8 0 8 a 1.60 0.063 a2 1.35 1.45 0.053 0.057 b 0.30 0.40 reference 0.012 0.016 c 0.17 0.007 d 15.95 16.05 0.628 0.632 d1 13.95 14.05 0.549 0.553 d3 12.00 reference 0.472 reference e 15.95 16.05 0.628 0.632 e1 13.95 14.05 0.549 0.553 e3 12.00 reference 0.472 reference e1 0.80 reference 0.031 reference l 0.50 0.75 0.019 0.030 n64 64 060198r0
preliminary psd813f family 117 part # mcu plds/decoders i/o memory other psd zpsd zpsd data path pld inputs ports flash program store jtag @ @ @ interface input micro ? cells otp eprom boot parallel isp 5 v 5 v 2.7 v output eeprom/eeprom boot isp flash micro ? cells 2nd flash boot isp cpld pld outputs sram periph. mode page (w/bb) security reg. pmu apd psd813f1 ZPSD813F1 ZPSD813F1v 8 plus1 73 24 16 19 8-bit 27 1024kb 256kb 16kb x x x x x x x x psd813f2 zpsd813f2 zpsd813f2v 8 plus1 73 24 16 19 8-bit 27 1024kb 256kb 16kb x x x x x x x x psd813f3 zpsd813f3 zpsd813f3v 8 plus1 73 24 16 19 8-bit 27 1024kb 16kb x x x x x x x x psd813f4 zpsd813f4 zpsd813f4v 8 plus1 73 24 16 19 8-bit 27 1024kb 256kb x x x x x x x x psd813f5 zpsd813f5 zpsd813f5v 8 plus1 73 24 16 19 8-bit 27 1024kb x x x x x x x x selector guide C psd813f family legend: zpsd = zero power version available at 4.5 v to 5.5 v v cc (example: zpsd311-15j). zpsdv = zero power version available at 2.7 v to 5.5 v v cc (example: zpsd311v-25j). 2.7 v to 3.6 v v cc on psd8xxf family. std = standard mcu interfaces supported (multiplexed and non-multiplexed). std-m = standard mcu interfaces supported (multiplexed only). plus = new intel 80c251 and philips 80c51xa supported plus all standard mcus. w/bb = battery backed-up sram. apd = automatic power down. selector guide
psd813f family preliminary 118 operating speed temperature part number (ns) package type range psd813f1-90j 90 52 pin pldcc comm l psd813f1-90ji 90 52 pin pldcc industrial psd813f1-90u 90 64 pin tqfp comm l psd813f1-90ui 90 64 pin tqfp industrial psd813f1-12j 120 52 pin pldcc comm l psd813f1-12ji 120 52 pin pldcc industrial psd813f1-12u 120 64 pin tqfp comm l psd813f1-12ui 120 64 pin tqfp industrial psd813f1-15j 150 52 pin pldcc comm l psd813f1-15ji 150 52 pin pldcc industrial psd813f1-15u 150 64 pin tqfp comm l psd813f1-15ui 150 64 pin tqfp industrial psd813f2-90j 90 52 pin pldcc comm l psd813f2-90ji 90 52 pin pldcc industrial psd813f2-90u 90 64 pin tqfp comm l psd813f2-90ui 90 64 pin tqfp industrial psd813f2-12j 120 52 pin pldcc comm l psd813f2-12ji 120 52 pin pldcc industrial psd813f2-12u 120 64 pin tqfp comm l psd813f2-12ui 120 64 pin tqfp industrial psd813f2-15j 150 52 pin pldcc comm l psd813f2-15ji 150 52 pin pldcc industrial psd813f2-15u 150 64 pin tqfp comm l psd813f2-15ui 150 64 pin tqfp industrial part number construction ordering information temperature (blank = commercial, i = industrial, m = military) package type speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) revision (blank = no revision) supply voltage (blank = 5v, v = 3 volt) base part number - see selector guide psd (wsi programmable system device) fam. power down feature (blank = standard, z = zero power feature) z psd -a -20 j i 413a2 v
preliminary psd813f family 119 operating speed temperature part number (ns) package type range psd813f3-90j 90 52 pin pldcc comm l psd813f3-90ji 90 52 pin pldcc industrial psd813f3-90u 90 64 pin tqfp comm l psd813f3-90ui 90 64 pin tqfp industrial psd813f3-12j 120 52 pin pldcc comm l psd813f3-12ji 120 52 pin pldcc industrial psd813f3-12u 120 64 pin tqfp comm l psd813f3-12ui 120 64 pin tqfp industrial psd813f3-15j 150 52 pin pldcc comm l psd813f3-15ji 150 52 pin pldcc industrial psd813f3-15u 150 64 pin tqfp comm l psd813f3-15ui 150 64 pin tqfp industrial psd813f4-90j 90 52 pin pldcc comm l psd813f4-90ji 90 52 pin pldcc industrial psd813f4-90u 90 64 pin tqfp comm l psd813f4-90ui 90 64 pin tqfp industrial psd813f4-12j 120 52 pin pldcc comm l psd813f4-12ji 120 52 pin pldcc industrial psd813f4-12u 120 64 pin tqfp comm l psd813f4-12ui 120 64 pin tqfp industrial psd813f4-15j 150 52 pin pldcc comm l psd813f4-15ji 150 52 pin pldcc industrial psd813f4-15u 150 64 pin tqfp comm l psd813f4-15ui 150 64 pin tqfp industrial psd813f5-90j 90 52 pin pldcc comm l psd813f5-90ji 90 52 pin pldcc industrial psd813f5-90u 90 64 pin tqfp comm l psd813f5-90ui 90 64 pin tqfp industrial psd813f5-12j 120 52 pin pldcc comm l psd813f5-12ji 120 52 pin pldcc industrial psd813f5-12u 120 64 pin tqfp comm l psd813f5-12ui 120 64 pin tqfp industrial psd813f5-15j 150 52 pin pldcc comm l psd813f5-15ji 150 52 pin pldcc industrial psd813f5-15u 150 64 pin tqfp comm l psd813f5-15ui 150 64 pin tqfp industrial ordering information
120 psd813f family preliminary operating speed temperature part number (ns) package type range ZPSD813F1-90j 90 52 pin pldcc comm l ZPSD813F1-90ji 90 52 pin pldcc industrial ZPSD813F1-90u 90 64 pin tqfp comm l ZPSD813F1-90ui 90 64 pin tqfp industrial ZPSD813F1-12j 120 52 pin pldcc comm l ZPSD813F1-12ji 120 52 pin pldcc industrial ZPSD813F1-12u 120 64 pin tqfp comm l ZPSD813F1-12ui 120 64 pin tqfp industrial ZPSD813F1-15j 150 52 pin pldcc comm l ZPSD813F1-15ji 150 52 pin pldcc industrial ZPSD813F1-15u 150 64 pin tqfp comm l ZPSD813F1-15ui 150 64 pin tqfp industrial ZPSD813F1v-15j 150 52 pin pldcc comm l ZPSD813F1v-15u 150 64 pin tqfp industrial ZPSD813F1v-20j 200 52 pin pldcc comm l ZPSD813F1v-20u 200 64 pin tqfp comm l ZPSD813F1v-20ji 200 52 pin pldcc industrial ZPSD813F1v-20ui 200 64 pin tqfp industrial zpsd813f2-90j 90 52 pin pldcc comm l zpsd813f2-90ji 90 52 pin pldcc industrial zpsd813f2-90u 90 64 pin tqfp comm l zpsd813f2-90ui 90 64 pin tqfp industrial zpsd813f2-12j 120 52 pin pldcc comm l zpsd813f2-12ji 120 52 pin pldcc industrial zpsd813f2-12u 120 64 pin tqfp comm l zpsd813f2-12ui 120 64 pin tqfp industrial zpsd813f2-15j 150 52 pin pldcc comm l zpsd813f2-15ji 150 52 pin pldcc industrial zpsd813f2-15u 150 64 pin tqfp comm l zpsd813f2-15ui 150 64 pin tqfp industrial zpsd813f2v-15j 150 52 pin pldcc comm l zpsd813f2v-15u 150 64 pin tqfp comm l zpsd813f2v-20j 200 52 pin pldcc comm l zpsd813f2v-20u 200 64 pin tqfp comm l zpsd813f2v-20ji 200 52 pin pldcc industrial zpsd813f2v-20ui 200 64 pin tqfp industrial zpsd813f3-90j 90 52 pin pldcc comm l zpsd813f3-90ji 90 52 pin pldcc industrial zpsd813f3-90u 90 64 pin tqfp comm l zpsd813f3-90ui 90 64 pin tqfp industrial zpsd813f3-12j 120 52 pin pldcc comm l zpsd813f3-12ji 120 52 pin pldcc industrial zpsd813f3-12u 120 64 pin tqfp comm l zpsd813f3-12ui 120 64 pin tqfp industrial zpsd813f3-15j 150 52 pin pldcc comm l zpsd813f3-15ji 150 52 pin pldcc industrial zpsd813f3-15u 150 64 pin tqfp comm l zpsd813f3-15ui 150 64 pin tqfp industrial ordering information
preliminary psd813f family 121 operating speed temperature part number (ns) package type range zpsd813f3v-15j 150 52 pin pldcc comm l zpsd813f3v-15u 150 64 pin tqfp comm l zpsd813f3v-20j 200 52 pin pldcc comm l zpsd813f3v-20u 200 64 pin tqfp comm l zpsd813f3v-20ji 200 52 pin pldcc industrial zpsd813f3v-20ui 200 64 pin tqfp industrial zpsd813f4-90j 90 52 pin pldcc comm l zpsd813f4-90ji 90 52 pin pldcc industrial zpsd813f4-90u 90 64 pin tqfp comm l zpsd813f4-90ui 90 64 pin tqfp industrial zpsd813f4-12j 120 52 pin pldcc comm l zpsd813f4-12ji 120 52 pin pldcc industrial zpsd813f4-12u 120 64 pin tqfp comm l zpsd813f4-12ui 120 64 pin tqfp industrial zpsd813f4-15j 150 52 pin pldcc comm l zpsd813f4-15ji 150 52 pin pldcc industrial zpsd813f4-15u 150 64 pin tqfp comm l zpsd813f4-15ui 150 64 pin tqfp industrial zpsd813f4v-15j 150 52 pin pldcc comm l zpsd813f4v-15u 150 64 pin tqfp comm l zpsd813f4v-20j 200 52 pin pldcc comm l zpsd813f4v-20u 200 64 pin tqfp comm l zpsd813f4v-20ji 200 52 pin pldcc industrial zpsd813f4v-20ui 200 64 pin tqfp industrial zpsd813f5-90j 90 52 pin pldcc comm l zpsd813f5-90ji 90 52 pin pldcc industrial zpsd813f5-90u 90 64 pin tqfp comm l zpsd813f5-90ui 90 64 pin tqfp industrial zpsd813f5-12j 120 52 pin pldcc comm l zpsd813f5-12ji 120 52 pin pldcc industrial zpsd813f5-12u 120 64 pin tqfp comm l zpsd813f5-12ui 120 64 pin tqfp industrial zpsd813f5-15j 150 52 pin pldcc comm l zpsd813f5-15ji 150 52 pin pldcc industrial zpsd813f5-15u 150 64 pin tqfp comm l zpsd813f5-15ui 150 64 pin tqfp industrial zpsd813f5v-15j 150 52 pin pldcc comm l zpsd813f5v-15u 150 64 pin tqfp comm l zpsd813f5v-20j 200 52 pin pldcc comm l zpsd813f5v-20u 200 64 pin tqfp comm l zpsd813f5v-20ji 200 52 pin pldcc industrial zpsd813f5v-20ui 200 64 pin tqfp industrial ordering information
psd813f family preliminary 122 temporary exceptions to specifications the following information describes exceptions to specifications contained in this data sheet. these exceptions will be corrected in future releases of psd813f products. please note the device markings for which these exceptions apply. for psd813f devices marked es3 on the topside, the following specification exceptions apply. 1. the turbo off adder parameter has changed (5v zpsd813fx devices only). normal operation when the 5v zpsd813f device is operated in non-turbo mode, the amount of propagation delay in the cpld, and the memory access times, are increased by the turbo off adder parameter of 10 nsec, as listed throughout the ac/dc parameter section. discrepancy the value of the turbo off adder for 5v zpsd813f devices has increased from 10 nsec to 15 nsec. when viewing the 5v ac/dc parameter specifications, replace any occurrence of 10 nsec for the turbo off adder parameter with 15 nsec. 2. the user code feature of ieee 1149.1 is not supported via the psd jtag channel. (psd813fx, zpsd813fx, and zpsd813fxv devices) normal operation the psd813f provides 32 bits of non-volatile memory (user code), to allow the user to store information. typical uses are product id, product software revision information, etc. read and write access is available through a stand-alone device programmer (like psdpro) or the ieee 1149.1 jtag channel. the microcontroller does not have access. discrepancy the user code information cannot be accessed through the psd jtag channel. however, it can be accessed using a device programmer (like psdpro). 3. initial enabling of software data protect (sdp) mode requires writing data to a reserved memory space. (psd813f1 and ZPSD813F1 only) normal operation the software data protect (sdp) mode for eeprom can be set when the microcontroller (mcu) writes a three byte command sequence to the eeprom per table 9. once sdp mode is set, any further writes to eeprom must be proceeded by these same three command bytes to unlock the eeprom per figure 3. this offers data protection much like that of flash memory. sdp mode may be enabled when the mcu initializes the system, and left on all the time for maximum protection. alternately, sdp mode may be disabled before writing blocks of data to eeprom, and enabled after writing. this method still offers good protection without the time penalty of writing aah, 55h, a0h before each set of data. the mcu can enable sdp mode by either of two methods: 1) write three command bytes and no data (aah,55h, a0h) as shown in table 9. 2) write three command bytes followed by one or more actual data bytes to be written into the eeprom (aah, 55h, a0h, data1, data2, .... data64), also shown in table 9 sdp mode is controlled by a programmable non-volatile (nvm) bit inside the psd. once sdp mode is enabled, it will stay enabled until the mcu or a device programmer erases the nvm bit. psd813f devices are shipped from waferscale with sdp mode not enabled.
preliminary psd813f family 123 discrepancy anytime the mcu changes the state of sdp mode from disabled to enabled, it must write three command bytes (aah, 55h, a0h), then write a single dummy byte to a reserved address space of 128 bytes in length. the dummy byte can be any pattern. the mcu should not use method 1 or method 2 shown above to enable sdp mode. this is only necessary when going from sdp mode disabled to sdp mode enabled. if sdp mode is already enabled (enabled from the mcu or a stand-alone device programmer), then the command sequences in table 9 of the data sheets may be used to write byte(s) into the eeprom (no dummy write to reserved space is needed). if the mcu disables sdp mode, then enables sdp mode again, a dummy write to the reserved address space is needed to get sdp mode enabled again. interim solution reserve an address range 128 bytes in length within an unused portion of eeprom. this 128-byte space can be in any of the four eeprom segments, and must begin on a 128-byte address boundary. to enable sdp mode (only after previously being disabled), the mcu must write the command sequence aah, 55h, a0h to any valid eeprom sector at addresses x555h, xaaah, x555h respectively. but then it must write a single dummy byte to the first location within the reserved 128-byte address space. example (you don t have to use these exact addresses or dummy byte value): aah >> 8555h 55h >> 8aaah a0h >> 8555h just like data psd813f sheet so far. eeh >> 8080h dummy byte eeh is written to reserved address block starting at 8080h (block is from 8080h to 80ffh). from this point forward, sdp mode is enabled, until disabled by the mcu or a device programmer. if you cannot locate 128 bytes of unused space in your eeprom memory map, then you can use populated eeprom memory. however, you must first read the existing 128 bytes in the reserved space, enable sdp mode with the single dummy write, then write the original 128 bytes back into the reserved address space. temporary exceptions to specifications (cont.)
psd813f family preliminary 124 revision data sheet date reason changes 10 nov 97 psd813f initial release 1 jul 98 data sheet minor changes updated 3 jul 98 data sheet minor changes updated 22 sep 98 data sheet page 18 c7h changed to e3h. updated page 27 c7h changed to e3h, c1h changed to e4h. page 14 eeprom changed to eprom 13 jan 99 data sheet major changes reorganization of information updated updated and expanded text for clarification and readability. changes to technical data and specifications as well. please disregard previous versions. following is a listing of major parameters and areas that have changed, added, or deleted: page 2: changed standby reference, added erase/write cycle info page 17: added notes 3 and 4 page 35: added text for blocking bits in pmmr2 page 69: deleted sleep mode feature page 71: major changes to figs 31 and 32 page 72: deleted register pmmr1 page 76: new info on jtag invocation page 78: changed v cc tolerance, ind temp page 79: changed y-axis in fig 34 page 80: changed y-axis in fig 34a page 82: added v oh1 , deleted sleep mode from i sb page 84: changed t arpw page 85: changed t ha , t cha , t coa , t is , t ih page 87: added column for turbo off, changed t avqv , t rhqx , t rlrh page 88: changed t wlwh , t wlmv , t whqv2 , t vcs ,t dvmv page 89: added column for turbo off, changed t avqv(pa) , t slqv(pa) , t dvqv(pa) , t wlqv(pa) page 90: deleted t lvdv1 , t pd5 , t bvbh , t bxbl , added note for reset while prog/erase page 91: added note 2 page 92: added v oh1 , deleted sleep mode from i sb page 93: changed t arpw page 94: changed t ha , t cha , t coa , t is , t ih page 96: added column for turbo off, changed t avqv page 97: changed t dvwh , t whdx , t wlwh , t wlmv , t q7vqv , changed t vcs , t dvmv , t avpv document revisions
preliminary psd813f family 125 revision data sheet date reason changes 13 jan 99 data sheet page 98: added column for turbo off, updated changed t avqv(pa) , t slqv(pa) , t dvqv(pa) page 99: deleted t lvdv1 , t pd5 , changed t bvbh , t bxbl , added note for reset while prog/erase page 100: added note 2 page 108: changed c vpp 29 jan 99 data sheet page 78: changed v cc tolerance, ind temp updated 11 feb 99 data sheet pages 84, 85, 86, 88, 89, 90, 91, 92: added -12 to ac updated dc specifications. 22 feb 99 data sheet page 117: added selector guide updated page 118: added part number construction and ordering information 12 may 99 data sheet page 18: added notes to table 9 updated page 22: page write timeout value changed. deleted reference to jtag and sdp mode. page 24: additional condition for writing to the otp row. page 29: additional condition for reading the main flash identifier. page 94 & 103: corrected spec for eeprom page write cycle time. changed spec for maximum eeprom write time. page 114: corrected signal name in figure 51. page 122: included exceptions to specifications for particular psd devices. 18 june 99 data sheet page 94: added more isc specifications: t isccf-p , t iscch-p , t isccl-p page 95: changed v oh specification. page 99: changed t rlrh , specification. page 100: changed t lxax , t wlwh , t whpv , t wlmv , t dvmv , specifications page 101: changed t dvqv(pa) , t wlqv(pa) , specifications page 103: added more isc specifications: t isccf-p , t iscch-p , t isccl-p page 122: changed specification exception number 3. removed reference to zpsd813fv since the exception does not apply to the 3 v psd. pages 79,95,96,97,99,100,101,103: changed the 3 v psd v cc range from 3 v 10% to 2.7 v to 3.6 v. 9 sept 99 data sheet pages 32, 33: changed mixed mode equations. updated pages 75, 93, 102, 110: changed reset requirement on power up. page 84: added isb to psd813f dc spec. page 94: changed isc port set up time. document revisions (cont.)
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